TXC-03305AIPQ Transwitch Corporation, TXC-03305AIPQ Datasheet - Page 53

• Manufacturer Part Number: TXC-03305AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03305AIPQ

• Lead Free Status / RoHS Status: Not Compliant

The transmit PMDL controller is disabled when a 0 is written to control bit EHT (bit 0) in register 3DH or when a
high is applied to the M13X lead or it is left floating. When disabled, the PMDL C-bits are sourced from either
the external DS3 C-bit interface when M13MODE = 0 (bit 0 register 02H) or from internal stuffing logic when
M13MODE = 1. The HDLC transmitter is enabled when a 1 is written to control bit EHT while a low is applied to
the M13X lead. When enabled, the transmit PMDL controller will transmit flags until data is placed in the trans-
mit FIFO. Up to 80 bytes can be placed in the transmit PMDL FIFO at once, but only 79 bytes are required. The
message bytes must be written into the transmit PMDL FIFO by writing into the TX PMDL FIFO register at 37H.
Bit 0 corresponds to the first bit transmitted. The transmit bytes are read from the transmit PMDL FIFO, a 16-bit
FCS is computed until the end of message is detected, and zero insertion (stuffing) is performed over the mes-
sage and FCS as needed. Please note that the stuffing function is performed on all of the bytes between the
opening and closing flags including the FCS. The FCS is calculated over the unstuffed raw data between, but
not including, the last bit in the opening flag and the first bit of the FCS. When the last byte of the message is
written into the FIFO, the microprocessor must set the end of message status bit EOM (bit 2) in register 3DH.
This allows the end of the message to be identified to the internal logic, so that it knows where to put the FCS.
The computed 16-bit FCS will be appended to the end of the message followed by at least one flag before
another message is transmitted. When the transmit PMDL FIFO is emptied without setting the EOM bit, the
FIFO will set an underflow indication value of 11 in interrupt request bits IRTXFS1 and IRTXFS0 (bits 2 and 1)
in register 2CH, and an abort character will be transmitted, thereby terminating the message. If the transmit
PMDL FIFO is emptied after the EOM bit is set, then the interrupt request bits IRTXFS(1-0) are not set, the
FCS is appended to the end of the message as appropriate and then flags are transmitted until another mes-
sage is transmitted.
The transmit HDLC controller provides interrupt request bits and corresponding interrupt request mask bits
related to the transmit PMDL FIFO status. Information such as underflow and fill status is provided by reading
interrupt request bits IRTXFS(1-0) (bits 2 and 1 in register 2CH).
Transmit PMDL FIFO service interrupts (IRTHIS bit in bit 0 of register 2CH) may be programmed to occur when
the transmit PMDL FIFO transitions from more than half full to half empty and/or when the last byte is sent, by
setting control bit THIE (bit 1) in register 3DH.
How an End User Might Transmit a PMDL Message
To transmit a PMDL message (79 bytes, excluding flags and FCS-16), first configure the transmitter to gener-
ate an interrupt at the end of message by writing a 0 to control bit THIE (bit 1) in register 3DH. Then write a 1 to
control bit EHT (bit 0) in register 3DH to enable the transmitter. The transmit PMDL controller will continue to
transmit flags until data is written into the transmit PMDL FIFO. Flags are sent in the selected C-bits in the C-bit
Parity format DS3 frame as a continuous idle pattern while the transmit PMDL controller is enabled and the
transmit PMDL FIFO is empty. If the transmit PMDL controller were not enabled then the PMDL C-bits would be
derived from either the external C-bit interface or the internal stuffing logic as dictated by the M13MODE bit (bit
0 in register 02H).
The desired message must be written by the microprocessor into the transmit PMDL FIFO by writing each byte
in turn into the TX PMDL FIFO register in register 37H. Bit 0 represents the first bit in the byte to be transmitted.
e. No hardware support is provided for receive frames that have a single octet address field. This type of
f. No hardware support is provided for receive frames that have an invalid service point access identifier.
frame is handled as a normal frame. User software can determine that the frame has a single octet
address field by reading it out of the FIFO and then choose to discard the data.
This type of frame is handled as a normal frame. Software can determine that the frame has an invalid
service point access identifier by reading it out of the FIFO and then choose to discard the data.
• The frame is written to the receive PMDL FIFO.
• The RX PMDL FIFO DEPTH register indicates the correct depth of the receive PMDL FIFO.
• The RX PMDL MESSAGE LENGTH register indicates the correct message length.
• The RX FCS ERROR Counter increments by 1.
DATA SHEET
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Ed. 4, September 2000
TXC-03305
TXC-03305-MB
M13X