TXC-03305AIPQ Transwitch Corporation, TXC-03305AIPQ Datasheet - Page 54

• Manufacturer Part Number: TXC-03305AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03305AIPQ

• Lead Free Status / RoHS Status: Not Compliant

TXC-03305-MB
Ed. 4, September 2000
M13X
TXC-03305
The bytes written into the TX PMDL FIFO register are transferred automatically into the transmit PMDL FIFO
by the M13X. After the microprocessor writes the last byte into the transmit PMDL FIFO, the microprocessor
sets the EOM (bit 2) in register 3DH to a 1. The transmit PMDL controller starts processing the message as the
PMDL FIFO is written, and continues processing until the FIFO is empty. If it encounters no EOM before the
PMDL FIFO becomes empty, the message is aborted. Since the EOM bit was set by the microprocessor, the
completion of the message will generate an interrupt, if not masked, as indicated by the interrupt request bit
IRTHIS (bit 0) in register 2CH. This latched status indication indicates that the message is complete and
another message can be written into the transmit PMDL FIFO by the microprocessor. After the FCS-16 is
transmitted (and stuffed by the transmit PMDL controller if needed), the HDLC link controller will start to send
flags again.
It is possible to send proprietary messages longer than 79 bytes (excluding FCS plus opening/closing flags). In
this case, the THIE bit should be set to a 1. Whenever the transmit PMDL FIFO transitions from more than half
full to half empty, then the IRTHIS bit will signal an interrupt request to tell the external microprocessor that
there is room to write more data into the transmit PMDL FIFO. This process continues until all of the message
has been loaded. Just as in the case above, when the last byte of the message is written by the microproces-
sor, the EOM bit is set by the microprocessor to identify the end of message to the internal logic so that the
FCS can be appended to it.
How an End User Might Receive a PMDL Message
To receive a PMDL message, first configure the receiver to generate an interrupt at the end of message and at
the full or overflow level of the receive PMDL FIFO by writing a 0 to control bit RHIE (bit 5) in register 3DH and
writing mask bits MIRRHIS(2-0) (bits 7 - 5 in register 35H) to 110 and MIRRXFS(1-0) (bits 4 and 3 in register
35H) to 11. Initialize the receive FIFO by reading the RX PMDL FIFO register in register 38H repeatedly until
the receive PMDL FIFO is emptied, which is indicated by RX PMDL FIFO DEPTH = 00H in register 3AH. Then
enable the receiver by writing a 1 to control bit EHR (bit 4) in register 3DH.
The receiver will generate an interrupt when the receive PMDL FIFO overflows, is full, or a message has been
received. A normal, valid received message is indicated by IRRHIS(2-0) = 010 and IRRXFS(1-0) = 00 or 01.
The end user must verify that this is the case. The RX PMDL MESSAGE LENGTH register is then read which
gives the end user the number of bytes in the message. The end user then reads that number of bytes from the
RX PMDL FIFO register by initiating multiple read cycles. The RX PMDL MESSAGE LENGTH register should
be read no more than 212 s after the IRRHIS(2-0) bits indicate that a message has been received to ensure
that a short message does not cause the RX PMDL MESSAGE LENGTH register to be overwritten before the
end user could read it.
Please note that the RX PMDL MESSAGE LENGTH register is updated when the end of message event indi-
cation is latched and an interrupt is generated, and will not be modified until it is read and cleared by the micro-
processor or if another completed message is received. The receive PMDL FIFO must be read for any type of
message termination (good FCS, bad FCS, abort, or invalid frame). If an abort occurs the remainder of the
HDLC message is discarded, requiring the end user to clear the receive FIFO of the portion of the message
indicated by the value in the RX PMDL MESSAGE LENGTH register. Care needs to be taken to determine the
location of an aborted message in the receive PMDL FIFO. This can ascertained by reading both the RX PMDL
MESSAGE LENGTH and RX PMDL FIFO DEPTH registers. An example is provided to show how to interpret
those two registers: An aborted frame is received and an interrupt is signaled via the IRRHIS(2-0) bits. The RX
PMDL FIFO DEPTH register is read and found to contain 0AH. The RX PMDL MESSAGE LENGTH register
content is read and found to be 07H. This means that there are 3 bytes from a previous frame that need to be
read out of the receive PMDL FIFO before the current 7-byte aborted frame can be read out.
Several short messages (such as might occur if several aborted messages are received in succession, or for
proprietary messaging) may be left in the receive FIFO and read out at a later time. This is accomplished by
storing the message length value read from the RX PMDL MESSAGE LENGTH register and the interrupt
requests read from IRLRHIS(2-0) and IRLRXFS(1-0) in a queue. The message boundaries and the validity of
the messages read from the FIFO may be determined from interrupt request and message length values. This
DATA SHEET
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