TXC-03305AIPQ Transwitch Corporation, TXC-03305AIPQ Datasheet - Page 86

• Manufacturer Part Number: TXC-03305AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03305AIPQ

• Lead Free Status / RoHS Status: Not Compliant

TXC-03305-MB
Ed. 4, September 2000
M13X
TXC-03305
Address
27
28
29
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
IRR3OOF
IRR3LOS
IRR3CKF
IRT3CKF
IRR3AIS
IRR3IDL
Symbol
IRNEW
IRLB27
IRLB23
IRLB19
IRLB15
IRLB11
IRLB28
IRLB24
IRLB20
IRLB16
IRLB12
IRSEF
IRXR2
IRXR1
IRLB7
IRLB3
IRLB8
IRLB4
New FEAC Message Interrupt Request Bit: The NEW condition is
defined as having received a NEW FEAC message. A NEW FEAC mes-
sage is understood to have been received when 5 consecutive and identi-
cal FEAC messages have been received. The NEW FEAC condition is
exited after a NEW FEAC message has been declared. When this bit and
its corresponding interrupt request mask bit in register 30H are both set to
1, the INT/IRQ lead is driven active. A microprocessor read cycle clears a
set interrupt request bit. The RISE and FALL bits in register 3FH control
whether this interrupt request bit is set on the entrance or exit of an alarm
condition, or both.
Care must be taken by the end user to ensure that the RX FEAC register
(1DH) is read within 8.5 ms (16 x 5 DS3 frames or 5 FEAC message times)
from the onset of this interrupt request to ensure that the FEAC message
that caused this interrupt does not get overwritten with a possible new
FEAC message.
Receive Loopback Interrupt Requests: The bits in these registers are
interrupt request bits for the corresponding remote loopback request bits in
register 0AH. The RISE and FALL bits in register 3FH control whether
these interrupt request bits are set on the entrance or exit of an alarm con-
dition, or both. If the corresponding interrupt request mask bit is set to a 1 in
register 30H then the INT/IRQ lead goes active to signal an interrupt
request to the external microprocessor when a bit in these registers
becomes set to 1. A microprocessor read cycle clears all set interrupt
request bits in the register that is read.
Severely Errored Frame Interrupt Request Bit: A severely errored frame
is defined as receiving 3 or more DS3 F-bits in error in a sliding window of
16 DS3 F-bits. An SEF defect is terminated when the receive DS3 signal is
in frame and there are fewer than 3 DS3 F-bit errors in 16 consecutive
F-bits (ANSI T1.231 sec. 7.1.2.2.2). When this bit and its corresponding
interrupt request mask bit in register 31H are both set to 1, the INT/IRQ
lead is driven active. A microprocessor read cycle clears a set interrupt
request bit. The RISE and FALL bits in register 3FH have no effect on the
functioning of this interrupt.
Receive Loopback Interrupt Requests: The bits in these registers are
interrupt request bits for the corresponding remote loopback request bits in
register 0BH. The RISE and FALL bits in register 3FH control whether
these interrupt request bits are set on the entrance or exit of an alarm con-
dition, or both. If the corresponding interrupt request mask bit is set to a 1 in
register 31H then the INT/IRQ lead goes active to signal an interrupt
request to the external microprocessor when a bit in these registers
becomes set to 1. A microprocessor read cycle clears all set interrupt
request bits in the register that is read.
DS3 Receive Alarms/Status Interrupt Requests: The bits in this register
location are interrupt request bits for the alarm/status bits listed in register
location 00H. When a bit in this register and its corresponding interrupt
request mask bit in register 32H are both set to 1, the INT/IRQ lead is
driven active. A microprocessor read cycle clears a set interrupt request bit.
The RISE and FALL bits in register 3FH control whether these interrupt
request bits are set on the entrance or exit of an alarm condition, or both.
DATA SHEET
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Description