TXC-03305AIPQ Transwitch Corporation, TXC-03305AIPQ Datasheet - Page 69

• Manufacturer Part Number: TXC-03305AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03305AIPQ

• Lead Free Status / RoHS Status: Not Compliant

MEMORY MAP DESCRIPTIONS
Address
00
Bit
7
6
5
4
3
Symbol
R3OOF
R3LOS
R3CKF
R3AIS
R3IDL
Receive DS3 Loss of Signal: A receive DS3 LOS alarm occurs, and this
bit is set to 1, when the incoming DS3 data (DS3DR) is stuck low for more
than 1020 DS3CR clock cycles. Recovery to 0 occurs when two or more
ones are detected in the incoming data bit stream. This bit is intended for
board diagnostics and is not meant to indicate a LOS on the DS3 line sig-
nal. This bit position is unlatched.
Receive DS3 Out of Frame: A receive OOF alarm occurs, and this bit is set
to 1, when three out of 16 F-bits are in error utilizing a sliding window of 16
DS3 F-bits, or one or more M-bits are in error in two consecutive frames.
Recovery to 0 occurs when the F framing pattern of 1001 is detected, and
the M framing pattern of 010 is detected for two consecutive frames. Recov-
ery takes approximately 0.95 milliseconds, worst case. This bit position is
unlatched. An OOF also inhibits the performance counters (04H, 05H, 06H,
1BH, 22H, 23H, 3BH, and 3CH).
Receive AIS Alarm Indication Signal: The M13X detects DS3 AIS by five
methods. The method of detection that drives the R3AIS alarm, and sets this
bit to 1, is selected by the states written to the three R3AISn bits in register
21H. This bit position is unlatched. When the M13X is configured to detect
one of the framed AIS signals (selected via bits 4-2 of register 21H), the
R3OOF bit (bit 6 of this register) should be examined to ensure that the
M13X is detecting DS3 frame.
Receive DS3 Idle Pattern Signal: A DS3 idle pattern signal has a valid M-
frame alignment channel, M-subframe alignment channel, and P-bit chan-
nel. The information bits are a 1100 sequence that starts with 11 after each
M-frame alignment, M-subframe alignment, X-bit, P-bit, and C-bit channels.
The C-bits (C7, C8, and C9) in M-subframe 3 are set to 0. A valid received
DS3 idle signal is detected, and this bit is set to 1, when the M13X detects
zeros for C7, C8, and C9 in subframe 3 and the 1100 sequence. The M13X
searches for the 1100 pattern sequence on a per DS3 frame basis. The
M13X can tolerate up to and including 5 errored 4-bit groups of the 1100
pattern per DS3 frame and still recognize the 1100 pattern as valid. If the
M13X detects 6 or more errored 4-bit groups of the 1100 pattern per DS3
frame the M13X will exit the R3IDL state and this bit will reset to 0. This bit
position is unlatched. A DS3 idle signal as defined in ANSI T1.107-1995 is
being received by the M13X device if this bit and bits 1 and 0 of this register
are all set to 1.
Receive DS3 Clock Failure: A receive DS3 clock failure alarm occurs, and
this bit is set to 1, when the receive clock (DS3CR) is stuck high or low for
6-7 XCK clock cycles. Recovery to 0 occurs when the DS3CR clock returns
for one cycle. The demultiplexer does not function when the receive clock is
lost. The DS3CR lead is still monitored for this alarm during DS3 local loop-
back (control bit 3LBK = 1), so that it may be necessary to set control bits
1TAIS1 and 1TAIS0 to 11 to prevent AIS insertions into the receive DS1
data stream. This bit position is unlatched.
DATA SHEET
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Description
Ed. 4, September 2000
TXC-03305
TXC-03305-MB
M13X