TXC-03305AIPQ Transwitch Corporation, TXC-03305AIPQ Datasheet - Page 92

• Manufacturer Part Number: TXC-03305AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03305AIPQ

• Lead Free Status / RoHS Status: Not Compliant

TXC-03305-MB
Ed. 4, September 2000
M13X
TXC-03305
35 (cont.)
Address
3A
3B
36
37
38
39
2-1
7-0
7-0
7-0
7-0
7-0
7-0
Bit
0
MIRTXFS1-
MIRTXFS0
MESSAGE
RX PMDL
RX PMDL
RX PMDL
TX PMDL
Reserved
MIRTHIS
LENGTH
RX FCS
Symbol
ERROR
Counter
DEPTH
FIFO
FIFO
FIFO
Transmit PMDL FIFO Interrupt Request Masks: If a bit and its corre-
sponding interrupt request bit in register 2CH are both set to a 1 then the
INT/IRQ lead goes active to signal an interrupt request to the external
microprocessor.
Transmit PMDL Interrupt Request Mask: If this bit and its corresponding
interrupt request bit in register 2CH are both set to a 1 then the INT/IRQ
lead goes active to signal an interrupt request to the external microproces-
sor.
Reserved: These bits are reserved and must always be written with 0s.
Transmit PMDL FIFO: The byte written into this location is written into the
transmit PMDL FIFO. Bit 0 corresponds to the first bit transmitted in an
HDLC message byte.
Receive PMDL FIFO: A read cycle for this location transfers one byte from
the receive PMDL FIFO to the data bus. Bit 0 corresponds to the first bit
received in the HDLC message. At initialization, the receive PMDL FIFO
must be cleared by reading this location the number of times indicated by
the RX PMDL FIFO DEPTH register (register 3AH) or until the RX PMDL
FIFO DEPTH register becomes 0.
Receive PMDL Message Length: This register is loaded with the number
of bytes in the last received frame if an end of message, abort, invalid
frame, or message received with bad FCS event occurs. The microproces-
sor must read this value before the end of another complete frame is
received. This register clears when read. The receive PMDL logic never
loads this register with a 0 when a valid PMDL frame is received (this is
done so that if a long frame is received, and the receive PMDL message
length ends up exceeding 255, and the IRRHIS(2-0) bits get set to 010 to
indicate a FIFO fill condition, then it can be known if an end of message
was really received.)
HDLC FIFO Depth: This register indicates the number of data bytes
present in the receive PMDL FIFO. The value is in binary. For example, the
value 0000 0000 indicates that the FIFO is empty, while a value 0111 1111
indicates that 127 bytes are present. This value is not reset when a new
frame is received. The previous frame length is stored in RX PMDL MES-
SAGE LENGTH, (bits 7- 0) in register 39H, which is updated every time a
new complete frame (good or errored) is received. This register value is
decreased by microprocessor reads of the RX PMDL FIFO register (regis-
ter 38H) only. At initialization, this location should read out as 00H. If it does
not, repeated reads of the RX PMDL FIFO register should be performed
until it does.
RX FCS Error Counter: A 16-bit saturating counter that counts the number
of PMDL messages that contained FCS errors. To read all 16 bits, read this
location to get the low byte and then read the common register location
(3EH) immediately after to get the high byte. The contents of this counter
should be disregarded when M13MODE = 1 or EHR = 0 or lead M13X is
high or floating. The counter is inhibited when DS3 loss of signal, out of
frame, AIS, or IDLE occurs. The counter is cleared when it is read by the
microprocessor. Single counts are not lost during a read cycle. When this
counter saturates, an interrupt request bit (IRFCSS) is set in register 2BH.
DATA SHEET
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Description