TXC-03305AIPQ Transwitch Corporation, TXC-03305AIPQ Datasheet - Page 6

• Manufacturer Part Number: TXC-03305AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03305AIPQ

• Lead Free Status / RoHS Status: Not Compliant

TXC-03305-MB
Ed. 4, September 2000
M13X
TXC-03305
modes. The M13X provides control bits in the memory map for selecting the remote loopback detection mech-
anism. The destuffing operation is still active during loopback request and operation. In addition to DS2 syn-
chronization, destuffing, and remote loopback request detection, the M13X also extracts the seven DS2 X-bits
and provides them to a register.
An option is provided that allows the received or transmitted DS1 channels to be monitored for loss of signal.
Receive data for each of the DS1 channels (DRn) is clocked out of the M13X on rising edges of the associated
clock signal (CRn), where n = 1 - 28. In addition, the M13X provides a stable DS1 clock signal for the data sig-
nals received during AIS periods. When the M13X lead is held low, dejitter buffers (DJBs) can be enabled via a
control bit to dejitter the receive DS1 outputs. The DJBs meet and exceed GR-499-CORE specifications.
In the transmit direction, DS1 transmit data (DTn) is clocked into the M13X on rising edges of the clock input
(CTn) for each of the 28 DS1 channels. A DS1 Input block, which consists of a FIFO and supporting logic, is
provided for each DS1 channel. Under software control, the M13X can invert the transmit data signals, or the
clock signals, for all 28 DS1 channels. The data inversion feature provides compatibility with certain T1 line
interface devices, while the clock inversion feature allows back-to-back M13X operation.
The DS1 Input block is also used to insert one of three idle patterns from a common generator into a DS1 bit
stream, under software control. The selection of the idle pattern is common to all 28 DS1 channels. The idle
patterns are: a QRS, an Extended Super Frame DS1 (ESF) format with all ones in DS0 channels 1 through 24,
and an AIS format (all ones).
Each DS1 signal is multiplexed into the respective DS2 frame, with the stuff bits inserted based on the fill level
of an internal FIFO. When the fill of the FIFO drops below half full, a stuff bit is inserted into the DS1 bit stream
in the DS2 signal. The DS2 signal is formed by combining four DS1 signals. In each frame there are 287 data
bit positions and one stuff bit per DS1 channel (for a DS1 total of 1152 bits) and 24 overhead bits, for a frame
total of 1176 bits. The overhead bits are used for framing, X-bit channel and stuff control.
The DS3 signal is partitioned into M-frames of 4760 bits each. The M-frames are divided into seven M-sub-
frames having 680 bits each. Each M-subframe is further divided into eight blocks of 85 bits each. Each block
uses 84 bits for payload and one bit for frame overhead. There are 56 overhead bits in each M-frame: the M-
frame alignment uses three bits, the M-subframe alignment (F-bits) uses 28 bits, 21 bits are defined as C-bits,
two bits are assigned for parity, and two bits are assigned for the X-bit channel. A frame synch input, TXFRM,
is provided and can optionally be used to align the DS3 overhead bits in the DS3DT output.
The DS3 frame is constructed and timed according to the operating mode, i.e., C-bit parity mode or M13 format
mode. In the C-bit parity mode, all seven of the DS2 stuff bits are always fixed as stuff, resulting in 7 pseudo
DS2 frames of 671 bits per DS2 frame in each DS3 frame, for a DS2 rate of 6.3062723 Mbit/s. Since stuffing
always occurs, the 21 C-bits are assigned for other functions, as shown in Figure 2. A C-bit interface is pro-
vided for transmitting 13 or 14 C-bits (C2, C3-depending on the state of bit 7 of register 19H (C3CLKI), C4, C5,
C6, C13, C14, C15, C16, C17, C18, C19, C20, C21). The external transmit C-bit interface consists of a serial
data input (CDT), an output clock (CCKT), a data link indicator pulse (CDCCT), and an output framing pulse
(CFMT). The data link indicator pulse identifies the location of the three data link bits, C13, C14, and C15. In
addition, a control bit is provided in the memory map which enables the M13X to generate an extra clock cycle
during the C3 bit time. When the M13X lead is tied low, the transmit PMDL controller can be enabled through
software control. The transmit PMDL controller supports transmission of HDLC (High Level Data Link Control)
encapsulated messages of arbitrary length. Interrupt request bits are provided for signaling transmit PMDL
FIFO and message status. When the transmit PMDL controller is enabled, C13, C14, and C15 on the transmit
C-bit interface are ignored; instead, C13, C14, and C15 are sourced from the transmit PMDL controller.
A receive C-bit interface is provided for extraction of 14 C-bits (C2, C3, C4, C5, C6, C13, C14, C15, C16, C17,
C18, C19, C20, C21). The receive C-bit interface consists of a serial data output (CDR), an output clock
(CCKR), a data link indicator pulse (CDCCR), and an output framing pulse (CFMR). The data link indicator
pulse identifies the location of the three data link C-bits, C13, C14, and C15.
DATA SHEET
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