TXC-03305AIPQ Transwitch Corporation, TXC-03305AIPQ Datasheet - Page 94

• Manufacturer Part Number: TXC-03305AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03305AIPQ

• Lead Free Status / RoHS Status: Not Compliant

TXC-03305-MB
Ed. 4, September 2000
M13X
TXC-03305
3D (cont.)
Address
3E
3F
7-0
7-2
Bit
0
1
0
Reserved
Symbol
RISE
FALL
EHT
CR
Enable HDLC Transmit Controller: A 1 enables the Transmit PMDL con-
troller. The PMDL C-bits in the transmit DS3 frame are derived from the
transmit PMDL controller. The transmitter will send flags when the transmit
PMDL FIFO is empty. The bytes are formatted into a message when the
transmit PMDL FIFO has bytes present, which is done by loading the TX
PMDL FIFO register (register 37H) repeatedly with the byte content of the
message to be sent. At the end of the message, a FCS is calculated and
transmitted. A 0 disables the transmit PMDL controller, clears the transmit
PMDL FIFO, and disables the PMDL transmit interrupts. In this case, the
PMDL C-bits in the transmit DS3 Frame are derived from the external trans-
mit C-bit interface (M13MODE = 0) or from the internal stuffing logic
(M13MODE = 1).
Common Register for High Byte of 16-Bit Counters: When the low byte
of a 16-bit counter is read, its high byte is simultaneously written to this reg-
ister and preserved for later access. In this way, the high byte and low byte
values correspond to the same instant in time.
Reserved: These bits are reserved and must always be written with a 0.
Rising Edge Sets Interrupt Request Bits: This control bit works in con-
junction with the FALL control bit (described below) for controlling the alarm
status bit transition used for setting the interrupt request bits. RISE=1
causes setting of the interrupt request bits on the 0 to 1 transition of the
alarm. Register 2CH is not affected by the setting of this bit. The interrupt
request bits in register 2CH are always set on the rising edge of the alarm
condition.
Falling Edge Sets Interrupt Request Bits: This control bit works in con-
junction with the RISE control bit (described above) for controlling the alarm
status bit transition used for setting the interrupt request bits. FALL=1
causes setting of the interrupt request bits on the 1 to 0 transition of the
alarm. Register 2CH is not affected by the setting of this bit. The interrupt
request bits in register 2CH are always set on the rising edge of the alarm
condition.
RISE
0
0
1
1
DATA SHEET
FALL
0
1
0
1
- 94 -
The appropriate interrupt request bits are disabled
from being set.
The appropriate interrupt request bits become set
when an alarm/condition is removed.
The appropriate interrupt request bits become set
when an alarm/condition is entered.
The appropriate interrupt request bits become set
when an alarm/condition is either entered or removed.
Description
Action