TXC-03305AIPQ Transwitch Corporation, TXC-03305AIPQ Datasheet - Page 88

• Manufacturer Part Number: TXC-03305AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03305AIPQ

• Lead Free Status / RoHS Status: Not Compliant

TXC-03305-MB
Ed. 4, September 2000
M13X
TXC-03305
Address
2C
7-5
Bit
IRRHIS2-
IRRHIS0
Symbol
Receive PMDL Interrupt Request: The following table lists the various
interrupt status indications associated with the receive PMDL message.
The significance of these bits is controlled by control bit RHIE (bit 5) in reg-
ister 3DH.
These are latched bits that clear when read by the microprocessor. If a bit
in this register is set to a 1 and the corresponding interrupt mask bit in reg-
ister 35H is set to a 1, then the INT/IRQ lead goes active to signal an inter-
rupt request to the external microprocessor. Codes of 110 and 101 are not
defined. When a condition occurs all three bits are updated at once. For
instance, when a start of message occurs, the bits are set to 001, and when
an end of message is received the bits will be changed from 001 to 010.
The bits are never forced to 000 by the internal logic. They only get set to
000 when a read is performed. The priority for detecting these alarms is:
IRRHIS2 IRRHIS1 IRRHIS0 RHIE
0
0
0
0
0
1
1
1
1
• Abort (highest)
• Invalid Frame Received
• FCS Error Received
• Start of Message Indication
• Valid Message Received
DATA SHEET
0
0
1
1
1
0
1
0
1
- 88 -
0
1
0
0
1
0
1
1
0
X
X
X
X
X
X
X
0
1
Description
Start of message indication
Valid message received; (FCS checked OK), or
the receive FIFO needs servicing (full or overflow).
Valid message received; (FCS checked OK), or
the receive FIFO needs servicing (half full or
more).
Message received with FCS error
Abort message received
Invalid Frame received. (i.e., frame with non-inte-
gral number of bytes or with number of bytes (after
destuffing) less than 5).
Unused Code.
Unused code.
Idle condition
Condition Present