NSK70721PE.C2 Intel, NSK70721PE.C2 Datasheet - Page 30

• Manufacturer Part Number: NSK70721PE.C2
• Manufacturer: Intel

Specifications of NSK70721PE.C2

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Supplier Unconfirmed

SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set
3.1.6.7
30
Register Address
1. See
Table 13. Micro-interruption Timer Register (MITR)
Table 14. Activation Sub-State Timer Registers
Table 15. Main Status Register (RD0)
A3-A0
1010
1011
1100
1101
1110
Figure 20
RD0—Main Status Register
Status Register bits serve the same purpose in Software Mode as the like-named individual pins in
Hardware mode.
and
B7:B0
Bit
B7
B6
B5
B4
B3
Bit
Figure 21
Timer Name
Timer Expiration (TMR_EXP). Set to 1by EDSP to indicate expiration of the Master Activation Timer.
•
•
TIP/RING polarity reversal (INVERT). Set to 0 by EDSP to indicate reversal of Tip and Ring signal
polarity at the receiver. Valid only in Active1 or Active2 states and only in framed modes 6 and 7.
Change of Frame Alignment (COFA). Indicates that re-acquisition of frame synchronization is in a
different position with respect to the last frame position. Does not cause interrupt. Latched event;
reset on read.
Loss Of Signal (LOS). Set to 1 by EDSP to indicate that Data Pump has entered into Inactive state.
•
WR2
•
Loop Number Indicator (LOOPID). Set to 0 or 1 by EDSP to indicate loop number 1 or number 2
respectively. Valid only in Active states, 0 in all others. LOOPID is set at the Master end of the loop
and selects the frame synchronizationsynchronization word format to encode the loop number. This
bit indicates the format of the received frame synchronization word at both the Master and the Slave.
The LOOPID function is supported only in framed modes 6 and 7.
Address: A<3:0> = 0000
Default: xxh (x=undefined)
Attributes: Read Only.
Eight Most Significant Bits (MSB) of the Micro-
interruption timer.
SMT1
SMT2
SMT3
SMT4
SMT5
Causes interrupt on changing from 0 to 1; masked by setting ACTMSK = 1 in register WR2
Latched event; reset on read, with persistence while in the Active state
Causes interrupt on transitions from 0 to 1 or 1 to 0; masked by setting LOSMSK = 1 in register
LOS is not a latched event
for the definition of these state transitions.
Table 15
lists the bit assignments in this register.
Default Value in Hex (Decimal)
Description
67(103)
Master
0A(10)
4E(78)
13(19)
41(65)
.
EDSP continuously updates the status
Status Bit Descriptions
1B(27)
4E(78)
13(19)
27(39)
40(64)
Slave
Pre-AGC
Master
Pre-EC
State Ended on Expiration
AAGC
PLL
EC
AAGC
Slave
Datasheet
PLL2
PLL1
Wait
EC