NSK70721PE.C2 Intel, NSK70721PE.C2 Datasheet - Page 4

• Manufacturer Part Number: NSK70721PE.C2
• Manufacturer: Intel

Specifications of NSK70721PE.C2

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Supplier Unconfirmed

SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set
Figures
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
SK70725/SK70721 Block Diagram ....................................................................... 7
Package Markings................................................................................................. 8
IAFE Pin Locations................................................................................................ 9
EDSP Pin Assignments....................................................................................... 11
EDSP/IAFE Interface – Relative Timing.............................................................. 21
MDSL System Data Transport (Framed Mode Shown) ...................................... 23
MDSL Frame (4,702 bits per frame example) ..................................................... 24
Framing with and without stuff bits(4,702 bits per frame example) ..................... 25
Clock/Data relationships: Transparent Operating Mode (#0), Sign First, Not
Scrambled36
Clock/Data relationships: Transparent Operating Mode (#1), Magnitude First, Not
Scrambled36
Clock/Data Relationships: Transparent Operating Mode (#2), Scrambled ......... 37
Clock/Data Relationships: Independent Operating Mode (#4), Sign First, Scram-
bler Disabled37
Clock/Data Relationships: Independent Operating Mode (#5), Scrambled......... 37
Clock/Data Relationships: Framed Mode (#6), Scrambled (7006/7010 bits per
frame)39
Clock/Data Relationships: Framed Mode (#7), Scrambled (4702/4706 bits per
frame)40
EMDP Clock Distribution In Master and Slave Modes ........................................ 41
EDSP Control and Status Signals (Stand-along Model) ..................................... 43
Activation State Machine for Modes 0,1,2,4 & 5 ................................................. 46
Activation State Machine for Modes 6 & 7 .......................................................... 47
MDSL Activating State Detail - Unframed Modes 0,1,2,4, and 5 ........................ 51
MDSL Activating State Detail - Framed Modes 6 and 7...................................... 52
MDSL Synchronization State Machine................................................................ 56
Micro-interruption as Defined in ETR-152........................................................... 58
Loopbacks........................................................................................................... 61
PCB Layout Guidelines
Typical Application (Software Mode)................................................................... 65
Typical Application (Optimized for noise free performance) ............................... 66
IAFE Normalized Pulse Amplitude Transmit Template ....................................... 70
Transmit Power Spectral Density—Upper Bound ............................................... 71
Typical Performance vs. Line Rate and Cable Gauge (Metric) ........................... 72
Typical Performance vs. Line Rate and Cable Gauge (English) ......................... 73
EDSP Clock and Data Interface Timing .............................................................. 76
EDSP Data Interface Timing ............................................................................... 77
RESET Timing (Processor Control Mode) .......................................................... 78
EDSP Read and Write Timing (Processor Control Mode.................................... 79
ACTREQ Signal Timing (Hardware Mode) ......................................................... 80
Data Pump Package Specifications .................................................................... 81
(Figure 26
for schematic) .............................................. 64
Datasheet