NSK70721PE.C2 Intel, NSK70721PE.C2 Datasheet - Page 41

• Manufacturer Part Number: NSK70721PE.C2
• Manufacturer: Intel

Specifications of NSK70721PE.C2

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Supplier Unconfirmed

3.2.3
Datasheet
Figure 16. EMDP Clock Distribution In Master and Slave Modes
A Master Data Pump derives its line transmit clock and data interface clocks from MSTR_CLK by
dividing it by 16. MSTR_CLK also provides a ±32 ppm accurate local training reference for the
receiver clock recovery VCXO before activation. When active, the Master Data Pump uses the
VCXO, as part of PLL, for clock recovery from the line. Since the Slave clock is synchronous
with the Master clock after activation, the result is that the transmit and receive signals and clocks
all operate at the same frequency. There is, however, an unknown phase difference between the
two clocks at the Master. All received clocks are subject, in addition, to degradation due to jitter
and wander.
At the Slave transceiver, SLAVE_CLK is used only to train the VCXO frequency within ±32 ppm
before activation. After activation, the Slave Data Pump derives the transmit clock, receiver
internal clock and data interface bit clock from the PLL locked to the received clock.
An internal FIFO is provided so that the receive data at the Master can be aligned with the bit clock
derived from the MSTR_CLK. This FIFO is disabled in Independent mode.
To select the clock and crystal frequencies required for a specific application, the required line rate
must first be calculated from the specified payload data rate. In the case of transparent and
Independent operating modes, the line rate would be equal to the payload data rate. In the case of
framed operating modes, line rate would be calculated as follows:
Operating mode 6, no bit stuffing: line rate = (7006/6992)*payload data rate.
Operating mode 6, with bit stuffing: line rate = (7010/6992)*payload data rate.
Operating mode 7, no bit stuffing: line rate = (4702/4688)*payload data rate.
Operating mode 7, with bit stuffing: line rate = (4706/4688)*payload data rate.
Control Modes
The EMDP includes an integrated, hardware controlled state machine unique to Intel DSL Data
Pumps. The hardware control mode allows the design of low cost, low power MDSL systems
which do not require the support of a microprocessor. Thus, in the hardware control mode no
programming is required. Where it is desirable to use the full capabilities of the EDSP, a
microprocessor interface provides access to the internal registers of the EDSP. The next two
sections describe both control modes.
(16 x bit rate,
+/- 32 ppm)
Clock
MSTR_CK
BIT_CK
Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721
1/16
MASTER
1/32
RD
FIFO
VCXO
WR
1/32
SLAVE
1/64
VCXO
32 x bit
clock
1/32
SLAVE_CK
BIT_CK
(16 x bit rate,
+/- 32 ppm)
Clock
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