XC3SD3400A-4FGG676C Xilinx Inc, XC3SD3400A-4FGG676C Datasheet - Page 66

• Manufacturer Part Number: XC3SD3400A-4FGG676C
• Description: FPGA, SPARTAN-3A, DSP, 676FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A DSPr

Specifications of XC3SD3400A-4FGG676C

• No. Of Logic Blocks: 5968
• No. Of Gates: 3400000
• No. Of Macrocells: 53712
• Family Type: Spartan-3A
• No. Of Speed Grades: 4
• Total Ram Bits: 2322432
• No. Of I/o's: 502
• Clock Management: DCM
• I/o Supply: RoHS Compliant
• Number Of Logic Elements/cells: 53712
• Number Of Labs/clbs: 5968
• Number Of I /o: 469
• Number Of Gates: 3400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 676-BBGA
• Package: 676FBGA
• Family Name: Spartan®-3A
• Device Logic Units: 53712
• Device System Gates: 3400000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 469
• Ram Bits: 2322432
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1539

CS484: 484-Ball Chip-Scale Ball Grid Array
The 484-ball chip-scale ball grid array, CS484, supports
both the XC3SD1800A and XC3SD3400A FPGAs. There
are no pinout differences between the two devices.
Table 63
by bank number and then by pin name. Pairs of pins that
form a differential I/O pair appear together in the table. The
table also shows the pin number for each pin and the pin
type, as defined earlier.
An electronic version of this package pinout table and
footprint diagram is available for download from the Xilinx
website at
www.xilinx.com/support/documentation/data_sheets/s3a_pin.zip
Pinout Table
Table 63: Spartan-3A DSP CS484 Pinout
DS610 (v3.0) October 4, 2010
Product Specification
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
lists all the CS484 package pins. They are sorted
IO_L30N_0
IO_L28N_0
IO_L25N_0
IO_L25P_0
IO_L24N_0/VREF_0
IO_L20P_0/GCLK10
IO_L18P_0/GCLK6
IP_0
IO_L15N_0
IP_0
IO_L11P_0
IO_L10P_0
IP_0
IO_L06P_0/VREF_0
IO_L06N_0
IP_0
IO_L07N_0
IO_0
IO_L30P_0
IO_L28P_0
IO_L24P_0
IO_L20N_0/GCLK11
IO_L18N_0/GCLK7
IO_L15P_0
IO_L11N_0
IO_L10N_0
IO_L03P_0
IO_L02N_0
Pin Name
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B3
B4
B6
B8
B9
B11
B13
B15
B17
B19
CS484
Ball
I/O
I/O
I/O
I/O
VREF
GCLK
GCLK
INPUT
I/O
INPUT
I/O
I/O
INPUT
VREF
I/O
INPUT
I/O
I/O
I/O
I/O
I/O
GCLK
GCLK
I/O
I/O
I/O
I/O
I/O
Type
www.xilinx.com
Table 63: Spartan-3A DSP CS484 Pinout (Cont’d)
Bank
Spartan-3A DSP FPGA Family: Pinout Descriptions
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO_L07P_0
IO_L29N_0
IP_0
IO_L21P_0
IO_L26P_0
IO_L22P_0
IO_L16P_0
IP_0
IP_0/VREF_0
IO_L14N_0
IO_L14P_0
IP_0
IO_L12N_0/VREF_0
IO_L08N_0
IO_L03N_0
IO_L02P_0/VREF_0
IO_L01N_0
IO_L29P_0
IO_L21N_0
IO_L26N_0
IO_L22N_0
IO_L16N_0
IO_L09N_0
IO_L12P_0
IO_L08P_0
IP_0
IP_0
IO_L01P_0
IP_0
IO_L31P_0/VREF_0
IO_L27N_0
IP_0
IO_L19N_0/GCLK9
IO_L17P_0/GCLK4
IO_L09P_0
IO_L05P_0
IO_L04P_0
IP_0
IO_L31N_0/PUDC_B
IO_L27P_0
IO_L23N_0
Pin Name
B20
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
D5
D6
D7
D9
D10
D13
D14
D15
D17
D18
D19
E6
E7
E8
E10
E11
E12
E13
E15
E16
E17
F7
F8
F9
CS484
Ball
I/O
I/O
INPUT
I/O
I/O
I/O
I/O
INPUT
VREF
I/O
I/O
INPUT
VREF
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
INPUT
I/O
INPUT
VREF
I/O
INPUT
GCLK
GCLK
I/O
I/O
I/O
INPUT
DUAL
I/O
I/O
Type
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