XC3SD3400A-4FGG676C Xilinx Inc, XC3SD3400A-4FGG676C Datasheet - Page 67

• Manufacturer Part Number: XC3SD3400A-4FGG676C
• Description: FPGA, SPARTAN-3A, DSP, 676FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A DSPr

Specifications of XC3SD3400A-4FGG676C

• No. Of Logic Blocks: 5968
• No. Of Gates: 3400000
• No. Of Macrocells: 53712
• Family Type: Spartan-3A
• No. Of Speed Grades: 4
• Total Ram Bits: 2322432
• No. Of I/o's: 502
• Clock Management: DCM
• I/o Supply: RoHS Compliant
• Number Of Logic Elements/cells: 53712
• Number Of Labs/clbs: 5968
• Number Of I /o: 469
• Number Of Gates: 3400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 676-BBGA
• Package: 676FBGA
• Family Name: Spartan®-3A
• Device Logic Units: 53712
• Device System Gates: 3400000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 469
• Ram Bits: 2322432
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1539

Table 63: Spartan-3A DSP CS484 Pinout (Cont’d)
DS610 (v3.0) October 4, 2010
Product Specification
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IO_L19P_0/GCLK8
IO_L17N_0/GCLK5
IP_0
IO_L13N_0
IO_L13P_0
IO_L05N_0
IO_L04N_0
IO_L23P_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
IO_L02N_1/LDC0
IP_L39N_1
IP_L39P_1/VREF_1
IO_L36P_1/A20
IO_L37P_1/A22
IO_L37N_1/A23
IO_L36N_1/A21
IO_L35N_1
IO_L33N_1
IO_L38N_1/A25
IO_L38P_1/A24
IO_L30N_1/A19
IO_L35P_1
IO_L33P_1
IO_L34P_1
IO_L34N_1
IO_L30P_1/A18
IP_L31N_1
IO_L28N_1
IO_L26P_1/A14
IO_L26N_1/A15
IO_L32N_1
IP_L31P_1/VREF_1
IO_L28P_1
IO_L29N_1/A17
IO_L32P_1
IO_L25N_1/A13
IP_L27P_1
Pin Name
F10
F11
F12
F13
F14
F15
F16
G8
B5
B10
B14
B18
E9
E14
AA22
C21
C22
D20
D21
D22
E19
E20
E22
F18
F19
F20
F21
F22
G17
G18
G19
G20
G22
H17
H18
H20
H21
H22
J17
J19
J20
J21
CS484
Ball
GCLK
GCLK
INPUT
I/O
I/O
I/O
I/O
I/O
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
DUAL
INPUT
VREF
DUAL
DUAL
DUAL
DUAL
I/O
I/O
DUAL
DUAL
DUAL
I/O
I/O
I/O
I/O
DUAL
INPUT
I/O
DUAL
DUAL
I/O
VREF
I/O
DUAL
I/O
DUAL
INPUT
Type
www.xilinx.com
Table 63: Spartan-3A DSP CS484 Pinout (Cont’d)
Bank
Spartan-3A DSP FPGA Family: Pinout Descriptions
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IP_L27N_1
IO_L29P_1/A16
IP_L23N_1
IO_L24N_1
IO_L24P_1
IO_L25P_1/A12
IO_L22N_1/A11
IO_L21N_1/RHCLK7
IP_L23P_1/VREF_1
IO_L20N_1/RHCLK5
IO_L20P_1/RHCLK4
IO_L22P_1/A10
IO_L18N_1/RHCLK1
IO_L21P_1/IRDY1/RHCLK6
IO_L19N_1/TRDY1/RHCLK3 M20
IO_L17N_1/A9
IO_L13P_1/A2
IO_L18P_1/RHCLK0
IO_L15N_1/A7
IO_L15P_1/A6
IO_L19P_1/RHCLK2
IO_L17P_1/A8
IO_L13N_1/A3
IP_L12N_1/VREF_1
IO_L10P_1
IP_L16N_1
IO_L14N_1/A5
IP_L12P_1
IO_L10N_1
IO_L07P_1
IO_L07N_1
IP_L16P_1/VREF_1
IO_L14P_1/A4
IO_L05N_1
IO_L05P_1
IO_L09N_1
IO_L11N_1/VREF_1
IO_L01P_1/HDC
IO_L01N_1/LDC2
IO_L09P_1
IP_L08N_1/VREF_1
IO_L11P_1
Pin Name
J22
K16
K17
K18
K19
K20
K22
L17
L18
L20
L21
L22
M17
M18
M22
N17
N18
N19
N20
N21
N22
P16
P17
P19
P20
P22
R17
R18
R19
R20
R21
R22
T17
T18
T20
T22
U18
U19
U20
U21
U22
CS484
Ball
INPUT
DUAL
INPUT
I/O
I/O
DUAL
DUAL
RHCLK
VREF
RHCLK
RHCLK
DUAL
RHCLK
RHCLK
RHCLK
DUAL
DUAL
RHCLK
DUAL
DUAL
RHCLK
DUAL
DUAL
VREF
I/O
INPUT
DUAL
INPUT
I/O
I/O
I/O
VREF
DUAL
I/O
I/O
I/O
VREF
DUAL
DUAL
I/O
VREF
I/O
Type
67