XC3SD3400A-4FGG676C Xilinx Inc, XC3SD3400A-4FGG676C Datasheet - Page 87

• Manufacturer Part Number: XC3SD3400A-4FGG676C
• Description: FPGA, SPARTAN-3A, DSP, 676FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A DSPr

Specifications of XC3SD3400A-4FGG676C

• No. Of Logic Blocks: 5968
• No. Of Gates: 3400000
• No. Of Macrocells: 53712
• Family Type: Spartan-3A
• No. Of Speed Grades: 4
• Total Ram Bits: 2322432
• No. Of I/o's: 502
• Clock Management: DCM
• I/o Supply: RoHS Compliant
• Number Of Logic Elements/cells: 53712
• Number Of Labs/clbs: 5968
• Number Of I /o: 469
• Number Of Gates: 3400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 676-BBGA
• Package: 676FBGA
• Family Name: Spartan®-3A
• Device Logic Units: 53712
• Device System Gates: 3400000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 469
• Ram Bits: 2322432
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1539

XC3SD3400A FPGA
Table 68
name. Pairs of pins that form a differential I/O pair appear together in the table.
pin and the pin type, as defined earlier.
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at:
www.xilinx.com/support/documentation/data_sheets/s3a_pin.zip.
Pinout Table
Note:
Table 68: Spartan-3A DSP FG676 Pinout for
XC3SD3400A FPGA
DS610 (v3.0) October 4, 2010
Product Specification
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The grayed boxes denote a difference between the XC3SD1800A and the XC3SD3400A devices.
lists all the FG676 package pins for the XC3SD3400A FPGA. They are sorted by bank number and then by pin
IO_L43N_0
IO_L39N_0
IO_L25P_0/GCLK4
IO_L12N_0
IP_0
IO_L43P_0
IO_L39P_0
IP_0
IO_L25N_0/GCLK5
IP_0
IO_L12P_0
IP_0/VREF_0
IO_L47N_0
IO_L46N_0
IO_L35N_0
IP_0
IO_L16N_0
IO_L08P_0
IP_0
IO_L52N_0/PUDC_B
IO_L47P_0
IO_L46P_0
IP_0/VREF_0
IO_L35P_0
IO_L27N_0/GCLK9
IP_0
IO_L16P_0
IO_L08N_0
IO_L02P_0/VREF_0
IO_L01P_0
XC3SD3400A Pin Name
FG676
Ball
G10
G11
G12
G13
G14
G15
G17
G19
G20
K11
K12
K14
K16
H10
H12
H13
H15
H17
H18
J10
J11
J12
J13
J14
J15
J16
J17
G8
G9
H9
I/O
I/O
GCLK
I/O
INPUT
I/O
I/O
INPUT
GCLK
INPUT
I/O
VREF
I/O
I/O
I/O
INPUT
I/O
I/O
INPUT
DUAL
I/O
I/O
VREF
I/O
GCLK
INPUT
I/O
I/O
VREF
I/O
Type
www.xilinx.com
Table 68: Spartan-3A DSP FG676 Pinout for
XC3SD3400A FPGA (Cont’d)
Bank
Spartan-3A DSP FPGA Family: Pinout Descriptions
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO_L48P_0
IO_L52P_0/VREF_0
IO_L31N_0
IO_L27P_0/GCLK8
IO_L24N_0
IO_L20P_0
IO_L13P_0
IO_L02N_0
IO_L01N_0
IO_L48N_0
IO_L37P_0
IP_0
IO_L31P_0
IO_L24P_0
IO_L20N_0/VREF_0
IO_L13N_0
IP_0
IO_L10P_0
IO_L44N_0
IP_0/VREF_0
IO_L40N_0
IO_L37N_0
IO_L34N_0
IO_L32N_0/VREF_0
IP_0
IO_L30P_0
IP_0/VREF_0
IO_L22P_0
IO_L21P_0
IO_L17P_0
IO_L11P_0
XC3SD3400A Pin Name
Table 68
also shows the pin number for each
FG676
Ball
E10
E11
E12
E14
E15
E17
E18
E21
D10
D11
D12
D13
D14
D16
D17
D18
D20
F12
F13
F14
F15
F17
F19
F20
E7
D6
D7
D8
D9
F7
F8
I/O
VREF
I/O
GCLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
I/O
I/O
VREF
I/O
INPUT
I/O
I/O
VREF
I/O
I/O
I/O
VREF
INPUT
I/O
VREF
I/O
I/O
I/O
I/O
Type
87