XC3SD3400A-4FGG676C Xilinx Inc, XC3SD3400A-4FGG676C Datasheet - Page 92

• Manufacturer Part Number: XC3SD3400A-4FGG676C
• Description: FPGA, SPARTAN-3A, DSP, 676FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A DSPr

Specifications of XC3SD3400A-4FGG676C

• No. Of Logic Blocks: 5968
• No. Of Gates: 3400000
• No. Of Macrocells: 53712
• Family Type: Spartan-3A
• No. Of Speed Grades: 4
• Total Ram Bits: 2322432
• No. Of I/o's: 502
• Clock Management: DCM
• I/o Supply: RoHS Compliant
• Number Of Logic Elements/cells: 53712
• Number Of Labs/clbs: 5968
• Number Of I /o: 469
• Number Of Gates: 3400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 676-BBGA
• Package: 676FBGA
• Family Name: Spartan®-3A
• Device Logic Units: 53712
• Device System Gates: 3400000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 469
• Ram Bits: 2322432
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1539

Table 68: Spartan-3A DSP FG676 Pinout for
XC3SD3400A FPGA (Cont’d)
DS610 (v3.0) October 4, 2010
Product Specification
Bank
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
VCCO_2
VCCO_2
VCCO_2
IO_L53P_3
IO_L53N_3
IP_3
IO_L57P_3
IO_L57N_3
IP_L50P_3
IP_L50N_3/VREF_3
IO_L52P_3
IO_L52N_3
IO_L63N_3
IO_L63P_3
IO_L47P_3
IO_L47N_3
IP_L46N_3
IO_L49N_3
IO_L59N_3
IO_L59P_3
IO_L61N_3
IO_L44P_3
IO_L44N_3
IP_L46P_3
IO_L42N_3
IO_L49P_3
IO_L51N_3
IO_L56P_3
IO_L56N_3
IO_L61P_3
IO_L38P_3
IO_L38N_3
IO_L42P_3
IO_L51P_3
IO_L48N_3
IO_L48P_3
IO_L36P_3/VREF_3
IO_L36N_3
IO_L37P_3
XC3SD3400A Pin Name
FG676
AB14
AB19
Ball
AB8
T10
W1
W2
W3
W4
W6
W7
Y1
Y2
Y3
Y5
Y6
V1
V2
V4
V5
V6
V7
V8
U1
U2
U3
U4
U5
U6
U7
U8
U9
R1
R2
R3
T3
T4
T5
T7
T9
VCCO
VCCO
VCCO
I/O
I/O
INPUT
I/O
I/O
INPUT
VREF
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
Type
www.xilinx.com
Table 68: Spartan-3A DSP FG676 Pinout for
XC3SD3400A FPGA (Cont’d)
Bank
Spartan-3A DSP FPGA Family: Pinout Descriptions
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO_L33N_3/IRDY2/LHCLK3
IO_L35P_3/TRDY2/LHCLK6
IO_L37N_3
IO_L40P_3
IO_L40N_3
IO_L45N_3
IO_L45P_3
IO_L43N_3
IO_L43P_3/VREF_3
IO_L33P_3/LHCLK2
IO_L34N_3/LHCLK5
IO_L34P_3/LHCLK4
IO_L39N_3
IO_L39P_3
IO_L41P_3
IO_L41N_3
IO_L35N_3/LHCLK7
IO_L31P_3
IO_L31N_3
IO_L30N_3
IO_L30P_3
IO_L32P_3/LHCLK0
IO_L32N_3/LHCLK1
IO_L29N_3/VREF_3
IO_L29P_3
IO_L27N_3
IO_L27P_3
IO_L28P_3
IO_L28N_3
IO_L26N_3
IO_L26P_3
IO_L21N_3
IO_L21P_3
IO_L25N_3
IO_L25P_3
IO_L18N_3
IO_L15N_3
IO_L15P_3
IP_L24N_3
XC3SD3400A Pin Name
FG676
M10
Ball
R10
P10
L10
M1
M2
M3
M4
M5
M6
M7
M8
M9
R4
R5
R6
R7
R8
R9
P1
P2
P3
P4
P6
P7
P8
P9
N1
N2
N4
N5
N6
N7
N9
K1
L3
L4
L7
L9
I/O
I/O
I/O
I/O
I/O
I/O
VREF
LHCLK
LHCLK
LHCLK
LHCLK
I/O
I/O
I/O
I/O
LHCLK
I/O
I/O
I/O
I/O
LHCLK
LHCLK
LHCLK
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
Type
92