SAA7118E NXP Semiconductors, SAA7118E Datasheet - Page 136

• Manufacturer Part Number: SAA7118E
• Manufacturer: NXP Semiconductors

Specifications of SAA7118E

• Adc/dac Resolution: 9b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 116. I port output format and configuration; register set A [93h[4:0]] and B [C3h[4:0]]
[1]
Table 117. Horizontal input window start; register set A [94h[7:0]; 95h[3:0]] and B [C4h[7:0]; C5h[3:0]]
[1]
Table 118. Horizontal input window length; register set A [96h[7:0]; 97h[3:0]] and B [C6h[7:0]; C7h[3:0]]
[1]
SAA7118_7
Product data sheet
I port output formats and configuration
4 : 2 : 2 double word formatting
4 : 1 : 1 double word formatting
4 : 2 : 0, only every 2nd line Y + C
output
4 : 1 : 0, only every 4th line Y + C
output
Y only
Not defined
Not defined
Not defined
No leading Y only line, before 1st Y + C
1 leading Y only line, before 1st Y + C
2 leading Y only lines, before 1st Y + C
3 leading Y only lines, before 1st Y + C
Horizontal input acquisition window
definition offset in X (horizontal)
direction
A minimum of ‘2’ should be kept, due
to a line counting mismatch
Odd offsets are changing the C
sequence in the output stream to
C
Maximum possible pixel offset = 4095
Horizontal input acquisition window
definition input window length in
X (horizontal) direction
No output
Odd lengths are allowed, but will be
rounded up to even lengths
Maximum possible number of input
pixels = 4095
R
-C
X = don’t care.
Reference for counting are luminance samples.
Reference for counting are luminance samples.
B
sequence
[1]
10.7.7 Subaddresses 94h to 9Bh
[1]
B
-C
B
B
-C
R
-C
R
R
B
output, in between Y only
-C
B
B
B
output, in between Y only
-C
-C
-C
Control bits
A [95h[3:0]] and
B [C5h[3:0]]
XO11 XO10 XO9
0
0
1
Control bits
A [97h[3:0]] and
B [C7h[3:0]]
XS11 XS10 XS9
0
0
1
R
R
R
R
line is output
line is output
line is output
line is output
0
0
1
0
0
1
Rev. 07 — 7 July 2008
0
0
1
0
0
1
Multistandard video decoder with adaptive comb filter
XO8
0
0
1
XS8
0
0
1
Control bits D4 to D0
FOI1
X
X
X
X
X
X
X
X
0
0
1
1
A [94h[7:0]] and B [C4h[7:0]]
XO7
0
0
1
A [96h[7:0]] and B [C6h[7:0]]
XS7
0
0
1
XO6
0
0
1
XS6
0
0
1
FOI0
X
X
X
X
X
X
X
X
0
1
0
1
XO5
XS5
0
0
1
0
0
1
XO4
0
0
1
XS4
0
0
1
FSI2
0
0
0
0
1
1
1
1
X
X
X
X
XO3
0
0
1
XS3
0
0
1
[1]
FSI1
0
0
1
1
0
0
1
1
X
X
X
X
SAA7118
© NXP B.V. 2008. All rights reserved.
XO2
1
XS2
0
0
0
0
1
XO1
1
1
1
XS1
0
0
1
FSI0
0
1
0
1
0
1
0
1
X
X
X
X
136 of 177
XO0
0
1
1
XS0
0
1
1