SAA7118E NXP Semiconductors, SAA7118E Datasheet - Page 63

SAA7118E

Manufacturer Part Number
SAA7118E
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SAA7118E

Adc/dac Resolution
9b
Screening Level
Commercial
Package Type
LBGA
Pin Count
156
Lead Free Status / RoHS Status
Compliant

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NXP Semiconductors
SAA7118_7
Product data sheet
8.6.1 Scaler output formatter (subaddresses 93h and C3h)
8.6.2 Video FIFO (subaddress 86h)
The output formatter organizes the packing into the output FIFO. The following formats
are available: Y-C
Y only (e.g. for raw samples). The formatting is controlled by FSI[2:0] 93h[2:0], FOI[1:0]
93h[4:3] and FYSK[93h[5]].
The data formats are defined on double words, or multiples, and are similar to the video
formats as recommended for PCI multimedia applications (compares to SAA7146A), but
planar formats are not supported.
FSI[2:0] defines the horizontal packing of the data, FOI[1:0] defines how many Y only lines
are expected, before a Y/C line will be formatted. If FYSK is set to logic 0 preceding Y only
lines will be skipped, and the output will always start with a Y/C line.
Additionally the output formatter limits the amplitude range of the video data (controlled by
ILLV[85h[5]]); see
Table 16.
Table 17.
Table 18.
The video FIFO at the scaler output contains 32 double words. That corresponds to
64 pixels in 16-bit Y-C
buffer, the actual available buffer capacity for the image port is much higher, and can
exceed beyond a video line.
The image port, and the video FIFO, can operate with the video source clock
(synchronous mode) or with an externally provided clock (asynchronous and burst mode),
as appropriate for the VGA controller or attached frame buffer.
The video FIFO provides 4 internal flags, reporting to what extent the FIFO is actually
filled.
Output format
Y-C
Y-C
Y only
Name
C
Yn
C
Limit step
ILLV[85h[5]]
0
1
B
R
n
n
B
B
-C
-C
R
R
4 : 2 : 2 C
4 : 1 : 1 C
Byte stream for different output formats
Explanation to
Limiting range on I port
Valid range
Decimal value
1 to 254
8 to 247
Byte sequence for 8-bit output modes
Y0
Explanation
C
Y (luminance) component, pixel number n = 0, 1, 2, 3 to 719
C
B
Table
-C
B
B
B
R
0 Y0
0 Y0
(B
(R
R
B
Y1
4 : 2 : 2, Y-C
-C
Rev. 07 — 7 July 2008
18.
Y) color difference component, pixel number n = 0, 2, 4 to 718
Y) color difference component, pixel number n = 0, 2, 4 to 718
R
Table 16
4 : 2 : 2 format. But as the entire scaler can act as a pipeline
C
C
Y2
R
R
Hexadecimal value
01 to FE
08 to F7
0 Y1
0 Y1
Multistandard video decoder with adaptive comb filter
Y3
B
-C
C
C
Y4
R
B
B
4 : 1 : 1, Y-C
2 Y2
4 Y2
Y5
C
C
Y6
R
R
Suppressed codes (hexadecimal value)
Lower range
00
00 to 07
2 Y3
4 Y3
B
Y7
-C
R
4 : 2 : 0, Y-C
C
Y4
Y8
B
4 Y4
Y5
Y9
C
Y6
Y10 Y11 Y12 Y13
SAA7118
R
Upper range
FF
F8 to FF
© NXP B.V. 2008. All rights reserved.
B
4 Y5
-C
R
Y7
4 : 1 : 0 and
C
C
B
B
63 of 177
6 Y6
8 Y8

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