SAA7118E NXP Semiconductors, SAA7118E Datasheet - Page 59

• Manufacturer Part Number: SAA7118E
• Manufacturer: NXP Semiconductors

Specifications of SAA7118E

• Adc/dac Resolution: 9b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SAA7118_7
Product data sheet
In
It should be noted that the equations of
the unscaled case, as the geometrical reference position for all conversions is the position
of the first line of the lower field; see
If there is no need for UP-LO and LO-UP conversion and the input field ID is the reference
for the back-end operation, then it is UP-LO = UP-UP and LO-UP = LO-LO and the
phase shift (PHO + 16) that can be skipped. This case is listed in
The SAA7118 supports 4 phase offset registers per task and component (luminance and
chrominance). The value of 20h represents a phase shift of one line.
The registers are assigned to the following events; e.g. subaddresses B8h to BBh:
Depending on the input signal (interlaced or non-interlaced) and the task processing
50 Hz or field reduced processing with one or two tasks (see examples in
Section
same.
Fig 40. Derivation of the phase related equations (example: interlace vertical scaling
•
•
•
•
Table 13
B8h: 00 = input field ID 0, task status bit D0 (toggle status; see
B9h: 01 = input field ID 0, task status bit D1
BAh: 10 = input field ID 1, task status bit D0
BBh: 11 = input field ID 1, task status bit D1
8.4.1.3), other combinations may also be possible, but the basic equations are the
field 1
upper
Offset =
A =
B =
C =
D = no offset = 0
down to
and
1
-- -
2
1
-- -
2
1
-- -
2
B
A
input line shift = 16
input line shift +
scale increment =
Table 14
1024
----------- -
32
3
5
, with field conversion)
lower
field 2
= 32 = 1 line shift
Rev. 07 — 7 July 2008
PHO is a usable common phase offset.
1
-- -
2
YSCY[15:0]
---------------------------- -
scale increment =
Multistandard video decoder with adaptive comb filter
64
case UP-UP
Table
field 1
Figure 40
C
13.
YSCY[15:0]
---------------------------- -
case LO-LO
64
produce an interpolated output, also for
field 2
D
+
16
case UP-LO
field 1
Table
Section
SAA7118
© NXP B.V. 2008. All rights reserved.
case LO-UP
14.
field 2
mhb548
8.4.1.3)
59 of 177
1
2
line