SAA7118E NXP Semiconductors, SAA7118E Datasheet - Page 55

• Manufacturer Part Number: SAA7118E
• Manufacturer: NXP Semiconductors

Specifications of SAA7118E

• Adc/dac Resolution: 9b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 12.
[1]
SAA7118_7
Product data sheet
Prescale
ratio
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
3
4
5
6
7
8
9
10
13
15
16
19
31
32
35
Resulting FIR function.
XACL[5:0] example of usage
8.4.2.2 Horizontal fine scaling (variable phase delay filter; subaddresses A8h to AFh and
XPSC
[5:0]
1
2
3
4
5
6
7
8
9
10
13
15
16
19
31
32
35
Recommended values
For lower bandwidth requirements
XACL[5:0]
0
2
(1 2 1)
4
(1 2 2 2 1)
7
(1 1 1 1 1 1 1 1)
8
(1 2 2 2 2 2 2 2 1)
8
(1 2 2 2 2 2 2 2 1)
8
(1 2 2 2 2 2 2 2 1)
15
(1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1)
15
(1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1)
16
(1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1)
16
31
32
32
32
63
63
D8h to DFh)
The horizontal fine scaling (VPD) should operate at scaling ratios between
(0.8 and 1.6), but can also be used for direct scaling in the range from
(theoretical) zoom 3.5 (restriction due to the internal data path architecture), without
prescaler.
In combination with the prescaler a compromise between sharpness impression and alias
can be found. This is signal source and application dependent.
For the luminance channel a filter structure with 10 taps is implemented, and for the
chrominance a filter with 4 taps.
1
4
[1]
1
8
XC2_1
0
1
1
0
1
1
1
0
0
1
1
0
1
1
1
1
1
[1]
1
8
1
1
1
[1]
16
16
16
[1]
[1]
[1]
Rev. 07 — 7 July 2008
XDCG[2:0]
0
2
3
3
4
4
4
4
4
5
5
5
6
6
6
7
7
1
1
16
16
1
Multistandard video decoder with adaptive comb filter
[1]
[1]
32
[1]
For higher bandwidth requirements
XACL[5:0]
0
1
(1 1)
3
(1 1 1 1)
4
(1 2 2 2 1)
7
(1 1 1 1 1 1 1 1)
7
(1 1 1 1 1 1 1 1)
7
(1 1 1 1 1 1 1 1)
8
(1 2 2 2 2 2 2 2 1)
8
(1 2 2 2 2 2 2 2 1)
8
(1 2 2 2 2 2 2 2 1)
16
16
16
32
32
32
63
1
2
[1]
1
4
1
[1]
XC2_1
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
1
8
[1]
1
1
1
8
8
8
1
1
1
[1]
[1]
[1]
16
16
16
[1]
[1]
[1]
XDCG[2:0]
0
1
2
3
3
3
3
4
4
4
5
5
5
6
6
6
7
SAA7118
1
© NXP B.V. 2008. All rights reserved.
7.999
1
FIR prefilter
PFY[1:0]/
PFUV[1:0]
0 to 2
0 to 2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
2
to
and 2
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