SAA7118E NXP Semiconductors, SAA7118E Datasheet - Page 2

• Manufacturer Part Number: SAA7118E
• Manufacturer: NXP Semiconductors

Specifications of SAA7118E

• Adc/dac Resolution: 9b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
2. Features
SAA7118_7
Product data sheet
2.1 Video acquisition/clock
2.2 Video decoder
2.3 Component video processing
The circuit is I
rate up to 400 kbit/s).
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Up to sixteen analog CVBS, split as desired (all of the CVBS inputs optionally can be
used to convert e.g. VSB signals)
Up to eight analog Y + C inputs, split as desired
Up to four analog component inputs, with embedded or separate sync, split as desired
Four on-chip anti-aliasing filters in front of the ADCs
Automatic Clamp Control (ACC) for CVBS, Y and C (or VSB) and component signals
Switchable white peak control
Four 9-bit low noise CMOS ADCs running at twice the oversampling rate (27 MHz)
Fully programmable static gain or Automatic Gain Control (AGC), matching to the
particular signal properties
On-chip line-locked clock generation in accordance with “ITU 601”
Requires only one crystal (32.11 MHz or 24.576 MHz) for all standards
Horizontal and vertical sync detection
Digital Phase-Locked Loop (PLL) for synchronization and clock generation from all
standards and non-standard video sources e.g. consumer grade VTR
Automatic detection of any supported color standard
Luminance and chrominance signal processing for PAL B, G, D, H, I and N,
combination PAL N, PAL M, NTSC M, NTSC-Japan, NTSC 4.43 and SECAM
Adaptive 2/4-line comb filter for two dimensional chrominance/luminance separation,
also with VTR signals
PAL delay line for correcting PAL phase errors
Brightness Contrast Saturation (BCS) adjustment, separately for composite and
baseband signals
User programmable sharpness control
Detection of copy-protected signals according to the Macrovision standard, indicating
level of protection
Independent gain and offset adjustment for raw data path
RGB component inputs
Y-P
Fast blanking between CVBS and synchronous component inputs
Digital RGB to Y-C
N
N
Increased luminance and chrominance bandwidth for all PAL and NTSC standards
Reduced cross color and cross luminance artefacts
B
-P
R
component inputs
2
C-bus controlled (full write/read capability for all programming registers, bit
B
-C
Rev. 07 — 7 July 2008
R
matrix
Multistandard video decoder with adaptive comb filter
SAA7118
© NXP B.V. 2008. All rights reserved.
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