LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 103

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

Operation
Mode Switching/Software Control
Software will execute P1284 negotiation and all operation prior to a data transfer phase under
programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake,
moving data between the FIFO and the ECP port only in the data transfer phase (modes 011 or 010).
Setting the mode to 011 or 010 will cause the hardware to initiate data transfer. If the port is in mode 000
or 001 it may switch to any other mode. If the port is not in mode 000 or 001 it can only be switched into
mode 000 or 001. The direction can only be changed in mode 001.
R/W
000:
001:
010:
011:
100:
101:
110:
111:
IRQ SELECTED
All Others
Standard Parallel Port Mode . In this mode the FIFO is reset and common collector drivers
are used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit
will not tri-state the output drivers in this mode.
PS/2 Parallel Port Mode. Same as above except that direction may be used to tri-state the
data lines and reading the data register returns the value on the data lines and not the value
in the data register. All drivers have active pull-ups (push-pull).
Parallel Port FIFO Mode. This is the same as 000 except that bytes are written or DMAed to
the FIFO. FIFO data is automatically transmitted using the standard parallel port protocol.
Note that this mode is only useful when direction is 0. All drivers have active pull-ups
(push-pull).
ECP Parallel Port Mode. In the forward direction (direction is 0) bytes placed into the
ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and transmitted
automatically to the peripheral using ECP Protocol. In the reverse direction (direction is 1)
bytes are moved from the ECP parallel port and packed into bytes in the ecpDFifo. All
drivers have active pull-ups (push-pull).
Selects EPP Mode: In this mode, EPP is selected if the EPP supported option is selected in
configuration register CR04 (Bits[1,0] and Bit[6]). All drivers have active pull-ups (push-pull).
Reserved
Test Mode. In this mode the FIFO may be written and read, but the data will not be
transmitted on the parallel port. All drivers have active pull-ups (push-pull).
Configuration Mode. In this mode the confgA, confgB registers are accessible at 0x400 and
0x401. All drivers have active pull-ups (push-pull).
15
14
11
10
9
7
5
Table 40B
BITS [5:3]
Table 40A - Extended Control Register
cnfgB
010
001
111
110
101
100
011
000
103
MODE
SELECTED
All Others
DMA
3
2
1
Table 40C
BITS [2:0]
cnfgB
011
010
001
000