LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 148

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

CR0B
CR0B can only be accessed in the configuration state and after the CSR has been initialized to 0BH.
CR0B indicates the Drive Rate table (Table 68) used for each drive. Refer to section CR1F for the
Drive Type register.
BIT NO.
4,5
6,7
0
1
2
3
IR Output Mux
Type: R/W
BIT NAME
Reserved
THR0
THR1
THR2
THR3
ECP FIFO Threshold/IR MUX
ECP FIFO Threshold 0.
ECP FIFO Threshold 1.
ECP FIFO Threshold 2.
ECP FIFO Threshold 3.
Read Only. A read returns 0.
These bits are used to select IR Output Mux Mode.
BIT7
0
0
1
1
Table 66 – CR0A
148
BIT6
0
1
0
1
Bits[7:6] = 00 on HARD RESET
DESCRIPTION
Default: 0x00 on VCC POR;
Active device to COM port (Default).
That is, depending on the mode of
Serial Port 2, use Pins 92, 94-100
for COM signals or use RXD2 and
TXD2 (pins 95 and 96) for IR.
When Serial Port 2 is inactive
(Power Down bit = 0), then TXD2
pin is low. The IRTX2 pin is low.
Active device to IR port. That is,
use IRRX2, IRTX2 (pins 61, 62).
When Serial Port 2 is inactive
(Power Down bit = 0), then IRTX2
pin is low. The TXD2 pin is low.
Reserved.
Outputs Inactive: TXD2 and IRTX2
are High-Z, regardless of mode of
UART2
powerdown bit.
and
MUX MODE
state
of
UART2