LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 140

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

CR00
CR00 can only be accessed in the configuration state and after the CSR has been initialized to 00H.
NOTE
power down bit does not disable the selected address range for the logical device. To disable the host
address registers the logical device’s base address must be set below 100h. Devices that are powered
down but still reside at a valid I/O base address will participate in Plug-and-Play range checking.
BIT NO.
4,5,6
1
0-2
: Power Down bits disable the respective logical device and associated pins, however the
3
7
Reserved
FDC Power
Reserved
Valid
Type: R/W
BIT NAME
1
FDC Power/Valid Configuration Cycle
Read Only. A read returns 0
A high level on this bit, supplies power to the FDC (default). A low
level on this bit puts the FDC in low power mode.
Read only. A read returns bit 5 as a 1 and bits 4 and 6 as a 0.
A high level on this software controlled bit can be used to indicate
that a valid configuration cycle has occurred. The control software
must take care to set this bit at the appropriate times. Set to zero
after power up. This bit has no effect on any other hardware in the
chip.
Table 56 – CR00
140
DESCRIPTION
Default: 0x28 on VCC POR