LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 111

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LPC47N227TQFP

Manufacturer Part Number
LPC47N227TQFP
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet

Specifications of LPC47N227TQFP

Lead Free Status / RoHS Status
Not Compliant

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results in the part remaining in powerdown state or exiting it.
Access to all other registers is possible without awakening the part. These registers can be accessed
during powerdown without changing the status of the part. A read from these registers will reflect the true
status as shown in the register description in the FDC description. A write to the part will result in the part
retaining the data and subsequently reflecting it when the part awakens. Accessing the part during
powerdown may cause an increase in the power consumption by the part. The part will revert back to its
low power mode when the access has been completed.
Pin Behavior
The LPC47N227 is specifically designed for systems in which power conservation is a primary concern.
This makes the behavior of the pins during powerdown very important.
The pins of the LPC47N227 can be divided into two major categories: system interface and floppy disk
drive interface. The floppy disk drive pins are disabled so that no power will be drawn through the part as
a result of any voltage applied to the pin within the part's power supply range. Most of the system
interface pins are left active to monitor system accesses that may wake up the part.
Note 1: Writing to the DOR or DSR does not wake up the part, however, writing any of the motor enable
bits or doing a software reset (via DOR or DSR reset bits) will wake up the part.
System Interface Pins
Table 45 gives the state of the interface pins in the powerdown state. Pins unaffected by the powerdown
are labeled "Unchanged".
BASE + ADDRESS
00H
01H
02H
03H
04H
06H
07H
07H
04H
05H
Table 45 – State of System Pins in Auto Powerdown
SYSTEM PINS
Access to these registers DOES NOT wake up the part
nLFRAME
Table 44 - PC/AT and PS/2 Available Registers
LAD[3:0]
nLPCPD
nLDRQ
Access to these registers wakes up the part
DOR (1)
DSR (1)
PC-AT
CCR
MSR
Data
DIR
AVAILABLE REGISTERS
----
----
---
---
PS/2 (MODEL 30)
111
DOR (1)
DSR (1)
CCR
MSR
STATE IN AUTO POWERDOWN
SRA
SRB
Data
DIR
---
---
Unchanged
Unchanged
Unchanged
Unchanged
ACCESS PERMITTED
R/W
R/W
---
W
---
W
R
R
R
R

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