LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 142

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

CR02 can only be accessed in the configuration state and after the CSR has been initialized to 02H.
NOTE
power down bit does not disable the selected address range for the logical device. To disable the host
address registers the logical device’s base address must be set below 100h. Devices that are powered
down but still reside at a valid I/O base address will participate in Plug-and-Play range checking.
BIT NO.
1
0-2
4-6
: Power Down bits disable the respective logical device and associated pins, however the
3
7
Reserved
UART1 Power
Down
Reserved
UART2 Power
Down
Type: R/W
BIT NAME
1
1
Read Only. A read returns “0”.
A high level on this bit, allows normal operation of the Primary
Serial Port (Default). A low level on this bit places the Primary
Serial Port into Power Down Mode.
Read Only. A read returns “0”.
A high level on this bit, allows normal operation of the Secondary
Serial Port, including the SCE/FIR block (Default). A low level on
this bit places the Secondary Serial Port including the SCE/FIR
block into Power Down Mode.
UART 1 and 2 Power
Table 58 – CR02
142
DESCRIPTION
Default: 0x08 on VCC POR;
Bit[7] = 0 on HARD RESET