LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 162

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

CR2B can only be accessed in the configuration state and after the CSR has been initialized to 2BH.
CR2B is used to set the SCE (FIR) base address ADR[10:3].
224 locations on 8-byte boundaries from 100H - 7F8H.
ADR8 to zero.
SCE Address Decoding: address bits A[15:11] must be ‘00000’ to access SCE registers. A[2:0] are
decoded as XXXb.
CR2C
CR2C can only be accessed in the configuration state and after the CSR has been initialized to 2CH.
Bits D[3:0] of this register are used to select the DMA for the SCE (FIR). Bits D[7:4] are Reserved.
Reserved bits cannot be written and return 0 when read. Any unselected DMA Request output (DRQ) is
in tristate.
BIT NO.
BIT NO.
3:0
7:4
0
1
2
3
4
5
6
7
DMA Select
Type: R/W
Type: R/W
BIT NAME
BIT NAME
Reserved
ADR10
ADR3
ADR4
ADR5
ADR6
ADR7
ADR8
ADR9
SCE (FIR) Base Address Register
SCE (FIR) DMA Select Register
FIR Base Address bits for decoder.
Read Only. A read returns 0.
BIT3 BIT2 BIT1 BIT0
0
0
0
0
0
1
1
.
.
Table 95 - CR2B
Table 96 - CR2C
0
0
0
0
1
1
1
.
.
162
0
0
1
1
0
1
1
.
.
To disable the SCE, set ADR10, ADR9 and
0
1
0
1
0
0
1
.
.
DESCRIPTION
DESCRIPTION
Default: 0x00 on VCC POR
Default: 0x00 on VCC POR
The SCE base address can be set to
DMA SELECTED
RESERVED
RESERVED
RESERVED
DMA1
DMA2
DMA3
NONE
.
.