LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 141

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

CR01 can only be accessed in the configuration state and after the CSR has been initialized to 01H.
NOTE
power down bit does not disable the selected address range for the logical device. To disable the host
address registers the logical device’s base address must be set below 100h. Devices that are powered
down but still reside at a valid I/O base address will participate in Plug-and-Play range checking.
BIT NO.
1
0,1
5,6
2
3
4
7
Power Down bits disable the respective logical device and associated pins, however the
Reserved
Parallel Port
Power
Parallel Port
Mode
Reserved
Reserved
Lock CRx
Type: R/W
BIT NAME
1
Read Only. A read returns “0”.
A high level on this bit, supplies power to the Parallel Port (Default).
A low level on this bit puts the Parallel Port in low power mode.
Parallel Port Mode. A high level on this bit, sets the Parallel Port for
Printer Mode (Default). A low level on this bit enables the Extended
Parallel port modes. Refer to Bits 0 and 1 of CR4
Read Only. A read returns “1”.
Read Only. A read returns “0”.
A high level on this bit enables the reading and writing of CR00 –
CR39 (Default). A low level on this bit disables the reading and
writing of CR00 – CR39. Note: once the Lock CRx bit is set to “0”,
this bit can only be set to “1” by a hard reset or power-up reset.
PP Power/Mode/CR Lock
Table 57 – CR01
141
DESCRIPTION
Default: 0x9C on VCC POR;
Bit[7] = 1 on HARD RESET