STPCC5HEBC STMicroelectronics, STPCC5HEBC Datasheet - Page 12

• Manufacturer Part Number: STPCC5HEBC
• Description: IC SYSTEM-ON-CHIP X86 388-PBGA
• Manufacturer: STMicroelectronics
• Series: -r

Specifications of STPCC5HEBC

• Applications: Set-Top Boxes, TV
• Core Processor: x86
• Program Memory Type: External Program Memory
• Controller Series: STPC® Consumer-II
• Ram Size: External
• Interface: EBI/EMI, I²C, IDE, ISA, Local Bus
• Number Of I /o: -
• Voltage - Supply: 2.45 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Not Compliant

PIN DESCRIPTION
12/93
BASIC CLOCKS AND RESETS
SYSRSETI#
SYSRSTO#
XTALI
XTALO
HCLK
DEV_CLK
DCLK
V
SDRAM CONTROLLER
MCLKI
MCLKO
CS#[1:0]
CS2# / MA11
CS3# / MA12 / BA1
BA[0]
MA[10:0]
MD[63:49]
MD[48:1]
MD[0]
RAS#[1:0]
CAS#[1:0]
MWE#
DQM[7:0]
PCI CONTROLLER
PCI_CLKI
PCI_CLKO
AD[31:0]
CBE[3:0]
FRAME#
IRDY#
TRDY#
LOCK#
DEVSEL#
STOP#
PAR
SERR#
PCIREQ#[2:0]
PCIGNT#[2:0]
PCI_INT#[3:0]
Note
Note
DD
_xxx_PLL
1
2
: These pins are must be connected to the 2.5 V power supply. They must not be connected to the 3.3 V supply.
: See
Signal Name
Table 2-3
1
for buffer type descriptions
Table 2-2. Definition of Signal Pins
Dir
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
Release 1.5 - January 29, 2002
SCHMITT_FT
BD8STRP_FT
ANA
OSCI13B
BD4STRP_FT
BT8TRP_TC
BD4STRP_FT
VDDCO
TLCHT_TC
BT8TRP_TC
BD8STRP_TC
BD16STARUQP_TC
BD16STARUQP_TC
BD8STRP_TC
BD16STARUQP_TC
BD8STRUP_FT
BD8TRP_TC
BD8STRUP_FT
BD16STARUQP_TC
BD16STARUQP_TC
BD16STARUQP_TC
BD8STRP_TC
TLCHT_FT
BT8TRP_TC
BD8PCIARP_FT
BD8PCIARP_FT
BD8PCIARP_FT
BD8PCIARP_FT
BD8PCIARP_FT
TLCHT_FT
BD8PCIARP_FT
BD8PCIARP_FT
BD8PCIARP_FT
BD8PCIARP_FT
BD8PCIARP_FT
BD8PCIARP_FT
BD4STRUP_FT
Buffer Type
2
System Power Good Input
System Reset Output
14.3 MHz Crystal Input- External
Oscillator Input
14.3 MHz Crystal Output
Host Clock (Test)
24 MHz Peripheral Clock (floppy drive)
27-135 MHz Graphics Dot Clock
Power Supply for PLL Clocks
Memory Clock Input
Memory Clock Output
DIMM Chip Select
DIMM Chip Select / Memory Address
DIMM Chip Select / Memory Address /
Bank Address
Bank Address
Memory Row & Column Address
Memory Data
Memory Data
Memory Data
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
33 MHz PCI Input Clock
33 MHz PCI O/P Clk (from internal PLL)
PCI Address / Data
Bus Commands / Byte Enables
Cycle Frame
Initiator Ready
Target Ready
PCI Lock
Device Select
Stop Transaction
Parity Signal Transactions
System Error
PCI Request
PCI Grant
PCI Interrupt Request
Description
Qty
12
15
48
32
1
1
1
1
1
1
1
1
1
2
1
1
1
1
2
2
1
8
1
1
1
1
1
1
1
1
1
1
3
3
4
4