STPCC5HEBC STMicroelectronics, STPCC5HEBC Datasheet - Page 80

• Manufacturer Part Number: STPCC5HEBC
• Description: IC SYSTEM-ON-CHIP X86 388-PBGA
• Manufacturer: STMicroelectronics
• Series: -r

Specifications of STPCC5HEBC

• Applications: Set-Top Boxes, TV
• Core Processor: x86
• Program Memory Type: External Program Memory
• Controller Series: STPC® Consumer-II
• Ram Size: External
• Interface: EBI/EMI, I²C, IDE, ISA, Local Bus
• Number Of I /o: -
• Voltage - Supply: 2.45 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Not Compliant

DESIGN GUIDELINES
The DIMM sockets should be populated starting
with the furthest DIMM from the STPC device first
(DIMM1). There are two types of DIMM devices;
single-row and dual-row. The dual-row devices
require two chip select signals to select between
the two rows. A STPC device with 4 chip select
control lines could control either 4 single-row
DIMMs or 2 dual-row DIMMs. When only 2 chip
select control lines are activated, only two single-
row DIMMs or one dual-row DIMM can be
controlled.
6.4.3.4. Summary
For unbuffered DIMMs the address/control signals
will be the most critical for timing. The simulations
show that for these signals the best way to drive
them is to use a parallel termination. For
applications where speed is not so critical series
termination can be used as this will save power.
Using a low impedance such as 50
critical traces is recommended as it both reduces
the delay and the overshoot.
The other memory interface signals will typically
be not as critical as the address/control signals.
Using lower impedance traces is also beneficial
80/93
MD[15:00],DQM[1:0]
MD[31:16],DQM[3:2]
MD[47:32],DQM[5:4]
MD[63:48],DQM[7:6]
Figure 6-22. Schematics for Optimum Data Bus Layout for DIMM
D[47:32]
D[15:00]
Figure 6-21. Optimum Data Bus Layout for DIMM
MD[31:00]
STPC
Release 1.5 - January 29, 2002
for these
SDRAM I/F
DIMM
STPC
When using DIMM modules, schematics have to
be done carefully in order to avoid data buses
completely crossing on the board. This has to be
checked at the library level. In order to achieve the
layout shown in
implement the crossing described in
The DQM signals must be exchanged using the
same order.
for the other signals but if their timing is not as
critical as the address/control signals they could
use the default value. Using a lower impedance
implies using wider traces which may have an
impact on the routing of the board.
The layout of this interface can be validated by an
electrical simulation
available on the STPC web site.
MD[63:32]
DIMM
D[15:00],DQM[1:0]
D[31:16],DQM[3:2]
D[47:32],DQM[5:4]
D[63:48],DQM[7:6]
Figure
D[31:16]
D[63:48]
using
6-21, schematics have to
the
IBIS
Figure
model
6-22.