STPCC5HEBC STMicroelectronics, STPCC5HEBC Datasheet - Page 2

• Manufacturer Part Number: STPCC5HEBC
• Description: IC SYSTEM-ON-CHIP X86 388-PBGA
• Manufacturer: STMicroelectronics
• Series: -r

Specifications of STPCC5HEBC

• Applications: Set-Top Boxes, TV
• Core Processor: x86
• Program Memory Type: External Program Memory
• Controller Series: STPC® Consumer-II
• Ram Size: External
• Interface: EBI/EMI, I²C, IDE, ISA, Local Bus
• Number Of I /o: -
• Voltage - Supply: 2.45 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Not Compliant

STPC
2/93
X86 Processor core
Fully static 32-bit five-stage pipeline, x86
Can access up to 4 GB of external memory.
8 Kbyte unified instruction and data cache
Parallel processing integral floating point unit,
Runs up to 100 MHz (x1) or 133 MHz (x2).
Fully static design for dynamic clock control.
Low power and system management modes.
Optimized design for 2.5 V operation.
SDRAM Controller
64-bit data bus.
Up to 100 MHz SDRAM clock speed.
Integrated system memory, graphic frame
Supports 2 MB up to 128 MB system
Supports 16-, 64-, and 128-Mbit SDRAMs.
Supports 8, 16, 32, 64, and 128 MB DIMMs.
Supports buffered, non buffered, and
Four-line write buffers for CPU to SDRAM
Four-line read prefetch buffers for PCI
Programmable latency
Programmable timing for SDRAM
Supports -8, -10, -12, -13, -15 memory parts
Supports memory hole between 1 MB and
2D Graphics Controller
64-bit windows accelerator.
Backward compatibility to SVGA standards.
Hardware acceleration for text, bitblts,
Up to 64 x 64 bit graphics hardware cursor.
Up to 4MB long linear frame buffer.
8-, 16-, 24- and 32-bit pixels.
Drivers availables for various OSes.
processor fully PC compatible.
with write back and write through capability.
with automatic power down.
memory and video frame memory.
memory.
registered DIMMs
and PCI to SDRAM cycles.
masters.
parameters.
8 MB for PCI/ISA busses.
transparent blts and fills.
®
CONSUMER-II
Release 1.5 - January 29, 2002
CRT Controller
Integrated 135 MHz triple RAMDAC allowing
Requires external frequency synthesizer and
8-bit, 16-bit, 24-bit pixels.
Interlaced or non-interlaced output.
Requires no external frequency synthesizer.
Requires only external reference source.
Video Input port
Accepts video inputs in ITU-R 601 mode.
Optional 2:1 decimator
Stores captured video in off setting area of
Video pass through to the TV output for full
HSYNC and B/T generation or lock onto
Video Pipeline
Two-tap interpolative horizontal filter.
Two-tap interpolative vertical filter.
Colour space conversion (RGB to YUV and
Programmable window size.
Chroma and colour keying for integrated
Video Output
NTSC-M; PAL-B, D, G, H, I, M, N encoding.
ITU-R 601 encoding with programmable
ITU-R 656 video output signal interface.
Four analog outputs in two configurations:
Flicker-free interlaced output.
Programmable two tap filter with gamma
Interlaced or non-interlaced operation mode.
Progressive to interlaced scan converter.
Cross colour reduction by specific trap
Power down mode available on each DAC.
for 1280 x 1024 x 75 Hz display.
reference sources.
the onboard frame buffer.
screen video images.
external video timing source.
YUV to RGB).
video overlay.
colour subcarrier frequencies.
- R,G,B + CVBS
- C,YS,CVBS1 + CVBS2
correction or three tap flicker filter.
filtering on luma within CVBS flow.