STPCC5HEBC STMicroelectronics, STPCC5HEBC Datasheet - Page 13

• Manufacturer Part Number: STPCC5HEBC
• Description: IC SYSTEM-ON-CHIP X86 388-PBGA
• Manufacturer: STMicroelectronics
• Series: -r

Specifications of STPCC5HEBC

• Applications: Set-Top Boxes, TV
• Core Processor: x86
• Program Memory Type: External Program Memory
• Controller Series: STPC® Consumer-II
• Ram Size: External
• Interface: EBI/EMI, I²C, IDE, ISA, Local Bus
• Number Of I /o: -
• Voltage - Supply: 2.45 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Not Compliant

ISA INTERFACE
ISA_CLK
ISA_CLK2X
OSC14M
LA[23:17]
SA[19:0]
SD[15:0]
ALE
MEMR#, MEMW#
SMEMR#, SMEMW#
IOR#, IOW#
MCS16#, IOCS16#
BHE#
ZWS#
REF#
MASTER#
AEN
IOCHCK#
IOCHRDY
ISAOE#
GPIOCS#
IRQ_MUX[3:0]
DREQ_MUX[1:0]
DACK_ENC[2:0]
TC
RTCAS
RMRTCCS#
KBCS#
RTCRW#
RTCDS#
LOCAL BUS INTERFACE
PA[23:0]
PD[15:0]
PRD1#,PRD0#
PWR1#,PWR0#
PRDY
FCS1#, FCS0#
IOCS#[3:0]
IDE CONTROLLER
DA[2:0]
DD[15:0]
Note
Note
1
2
: These pins are must be connected to the 2.5 V power supply. They must not be connected to the 3.3 V supply.
: See
Signal Name
Table 2-3
for buffer type descriptions
Table 2-2. Definition of Signal Pins
Dir
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
Release 1.5 - January 29, 2002
BT8TRP_TC
BT8TRP_TC
BD8STRP_FT
BD8STRUP_FT
BD8STRUP_FT
BD8STRP_FT
BD4STRP_FT
BD8STRUP_FT
BD8STRP_FT
BD8STRUP_FT
BD4STRUP_FT
BD8STRUP_FT
BD4STRP_FT
BD8STRP_FT
BD4STRUP_FT
BD8STRUP_FT
BD4STRUP_FT
BD8STRUP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD8STRP_FT
BD4STRUP_FT
BD4STRUP_FT
BD8STRUP_FT
BD4STRP_FT
BD8STRUP_FT
BD8STRUP_FT
BD8STRUP_FT
Buffer Type
2
ISA Clock Output
Multiplexer Select Line For IPC
ISA Clock x2 Output
Multiplexer Select Line For IPC
ISA bus synchronisation clock
Unlatched Address
Latched Address
Data Bus
Address Latch Enable
Memory Read and Write
System MemoryRead and Write
I/O Read and Write
Memory and I/O ChipSelect16
System Bus High Enable
Zero Wait State
Refresh Cycle.
Add On Card Owns Bus
Address Enable
I/O Channel Check.
I/O Channel Read
ISA/IDE Selection
General Purpose Chip Select
Time-Multiplexed Interrupt Request
Time-Multiplexed DMA Request
Encoded DMA Acknowledge
ISA Terminal Count
Real Time Clock Address Strobe
ROM/RTC Chip Select
Keyboard Chip Select
RTC Read/Write
RTC Data Strobe
Address Bus
Data Bus
Peripheral Read Control
Peripheral Write Control
Data Ready
Flash Chip Select
I/O Chip Select
Address Bus
Data Bus
Description
PIN DESCRIPTION
Qty
20
16
24
16
16
13/93
1
1
1
7
1
2
2
2
2
1
1
1
1
1
1
1
1
1
4
2
3
1
1
1
1
1
1
2
2
1
2
4
3