MC9S08GT60ACFDE Freescale, MC9S08GT60ACFDE Datasheet - Page 101
MC9S08GT60ACFDE
Manufacturer Part Number
MC9S08GT60ACFDE
Description
Manufacturer
Freescale
Datasheet
1.MC9S08GT60ACFDE.pdf
(302 pages)
Specifications of MC9S08GT60ACFDE
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
40MHz
Interface Type
I2C/SCI/SPI
Total Internal Ram Size
4KB
# I/os (max)
39
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
1.8/2.08V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
QFN EP
Program Memory Type
Flash
Program Memory Size
60KB
Lead Free Status / RoHS Status
Compliant
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PTGPE[7:0]
PTGD[7:0]
Reset
Reset
Field
Field
7:0
7:0
W
W
R
R
PTGPE7
PTGD7
Port PTG Data Register Bits — For port G pins that are inputs, reads return the logic level on the pin. For port
G pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port G pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTGD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
Pullup Enable for Port G Bits — For port G pins that are inputs, these read/write control bits determine whether
internal pullup devices are enabled. For port G pins that are configured as outputs, these bits are ignored and
the internal pullup devices are disabled.
0 Internal pullup device disabled.
1 Internal pullup device enabled.
0
0
7
7
PTGPE6
PTGD6
0
0
6
6
Figure 6-34. Pullup Enable for Port G (PTGPE)
Figure 6-33. Port PTG Data Register (PTGD)
Table 6-26. PTGPE Field Descriptions
Table 6-25. PTGD Field Descriptions
PTGPE5
PTGD5
MC9S08GB60A Data Sheet, Rev. 2
0
0
5
5
PTGPE4
PTGD4
0
0
4
4
Description
Description
PTGPE3
PTGD3
3
0
3
0
PTGPE2
PTGD2
0
0
2
2
Chapter 6 Parallel Input/Output
PTGPE1
PTGD1
0
0
1
1
PTGPE0
PTGD0
0
0
0
0
101
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