MC9S08GT60ACFDE Freescale, MC9S08GT60ACFDE Datasheet - Page 176

• Manufacturer Part Number: MC9S08GT60ACFDE
• Manufacturer: Freescale

Specifications of MC9S08GT60ACFDE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8/2.08V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: QFN EP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

Serial Communications Interface (S08SCIV1)
11.2
The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for
transmit/receive data.
Refer to the direct-page register summary in the
assignments for all SCI registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
11.2.1
This pair of registers controls the prescale divisor for SCI baud rate generation. To update the 13-bit baud
rate setting [SBR12:SBR0], first write to SCIxBDH to buffer the high half of the new value and then write
to SCIxBDL. The working value in SCIxBDH does not change until SCIxBDL is written.
SCIxBDL is reset to a non-zero value, so after reset the baud rate generator remains disabled until the first
time the receiver or transmitter is enabled (RE or TE bits in SCIxC2 are written to 1).
176
SBR[12:8]
SBR[7:0]
Reset
Reset
Field
Field
4:0
7:0
W
W
R
R
Register Definition
SBR7
SCI Baud Rate Registers (SCIxBDH, SCIxBHL)
Baud Rate Modulo Divisor — These 13 bits are referred to collectively as BR, and they set the modulo divide
rate for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to reduce supply
current. When BR = 1 to 8191, the SCI baud rate = BUSCLK/(16×BR). See also BR bits in
Baud Rate Modulo Divisor — These 13 bits are referred to collectively as BR, and they set the modulo divide
rate for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to reduce supply
current. When BR = 1 to 8191, the SCI baud rate = BUSCLK/(16×BR). See also BR bits in
0
0
0
7
7
= Unimplemented or Reserved
SBR6
0
0
0
6
6
Table 11-1. SCIxBDH Register Field Descriptions
Table 11-2. SCIxBDL Register Field Descriptions
Figure 11-4. SCI Baud Rate Register (SCIxBDH)
Figure 11-5. SCI Baud Rate Register (SCIxBDL)
SBR5
MC9S08GB60A Data Sheet, Rev. 2
0
0
0
5
5
Memory
SBR12
SBR4
0
0
4
4
Description
Description
chapter of this data sheet for the absolute address
SBR11
SBR3
3
0
3
0
SBR10
SBR2
0
1
2
2
Freescale Semiconductor
SBR9
SBR1
0
0
1
1
Table
Table
11-2.
11-1.
SBR8
SBR0
0
0
0
0