MC9S08GT60ACFDE Freescale, MC9S08GT60ACFDE Datasheet - Page 79

• Manufacturer Part Number: MC9S08GT60ACFDE
• Manufacturer: Freescale

Specifications of MC9S08GT60ACFDE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8/2.08V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: QFN EP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

1
5.8.7
Freescale Semiconductor
This bit can be written only one time after reset. Additional writes are ignored.
LVDACK
Reset
LVDRE
LVDSE
LVDIE
LVDE
Field
LVDF
7
6
5
4
3
2
W
R
System Power Management Status and Control 1 Register (SPMSC1)
LVDF
Low-Voltage Detect Flag — Provided LVDE = 1, this read-only status bit indicates a low-voltage detect event.
Low-Voltage Detect Acknowledge — This write-only bit is used to acknowledge low voltage detection errors
(write 1 to clear LVDF). Reads always return 0.
Low-Voltage Detect Interrupt Enable — This read/write bit enables hardware interrupt requests for LVDF.
0 Hardware interrupt disabled (use polling).
1 Request a hardware interrupt when LVDF = 1.
Low-Voltage Detect Reset Enable — This read/write bit enables LVDF events to generate a hardware reset
(provided LVDE = 1).
0 LVDF does not generate hardware resets.
1 Force an MCU reset when LVDF = 1.
Low-Voltage Detect Stop Enable — Provided LVDE = 1, this read/write bit determines whether the low-voltage
detect function operates when the MCU is in stop mode.
0 Low-voltage detect disabled during stop mode.
1 Low-voltage detect enabled during stop mode.
Low-Voltage Detect Enable — This read/write bit enables low-voltage detect logic and qualifies the operation
of other bits in this register.
0 LVD logic disabled.
1 LVD logic enabled.
Figure 5-9. System Power Management Status and Control 1 Register (SPMSC1)
0
7
= Unimplemented or Reserved
LVDACK
0
0
6
Table 5-10. SPMSC1 Field Descriptions
LVDIE
MC9S08GB60A Data Sheet, Rev. 2
0
5
LVDRE
1
4
1
Description
LVDSE
Chapter 5 Resets, Interrupts, and System Configuration
3
1
(1)
LVDE
1
2
(1)
0
0
1
0
0
0
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