MC9S08GT60ACFDE Freescale, MC9S08GT60ACFDE Datasheet - Page 220
MC9S08GT60ACFDE
Manufacturer Part Number
MC9S08GT60ACFDE
Description
Manufacturer
Freescale
Datasheet
1.MC9S08GT60ACFDE.pdf
(302 pages)
Specifications of MC9S08GT60ACFDE
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
40MHz
Interface Type
I2C/SCI/SPI
Total Internal Ram Size
4KB
# I/os (max)
39
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
1.8/2.08V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
QFN EP
Program Memory Type
Flash
Program Memory Size
60KB
Lead Free Status / RoHS Status
Compliant
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Inter-Integrated Circuit (S08IICV1)
13.7
220
1.
2.
3.
4.
1.
2.
3.
4.
5.
6.
7.
Write: IICA
— to set the slave address
Write: IICC
— to enable IIC and interrupts
Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data
Initialize RAM variables used to achieve the routine shown in
Write: IICF
— to set the IIC baud rate (example provided in this chapter)
Write: IICC
— to enable IIC and interrupts
Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data
Initialize RAM variables used to achieve the routine shown in
Write: IICC
— to enable TX
Write: IICC
— to enable MST (master mode)
Write: IICD
— with the address of the target slave. (The LSB of this byte will determine whether the communication is
The routine shown in
incoming IIC message that contains the proper address will begin IIC communication. For master operation,
communication must be initiated by writing to the IICD register.
Initialization/Application Information
IICC
IICD
IICA
IICS
IICF
master receive or transmit.)
Address to which the module will respond when addressed as a slave (in slave mode)
Data register; Write to transmit IIC data read to read IIC data
Baud rate = BUSCLK / (2 x MULT x (SCL DIVIDER))
Module configuration
Module status flags
IICEN
TCF
MULT
Figure 13-11
IICIE
IAAS
Figure 13-10. IIC Module Quick Start
BUSY
MST
Module Initialization (Master)
MC9S08GB60A Data Sheet, Rev. 2
Module Initialization (Slave)
can handle both master and slave IIC operations. For slave operation, an
Register Model
ARBL
Module Use
TX
ADDR
DATA
TXAK
0
ICR
Figure 13-11
Figure 13-11
RSTA
SRW
IICIF
0
RXAK
0
0
Freescale Semiconductor
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