MC9S08GT60ACFDE Freescale, MC9S08GT60ACFDE Datasheet - Page 164
MC9S08GT60ACFDE
Manufacturer Part Number
MC9S08GT60ACFDE
Description
Manufacturer
Freescale
Datasheet
1.MC9S08GT60ACFDE.pdf
(302 pages)
Specifications of MC9S08GT60ACFDE
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
40MHz
Interface Type
I2C/SCI/SPI
Total Internal Ram Size
4KB
# I/os (max)
39
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
1.8/2.08V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
QFN EP
Program Memory Type
Flash
Program Memory Size
60KB
Lead Free Status / RoHS Status
Compliant
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Timer/PWM (TPM)
10.6.4
For channels that are configured for PWM operation, there are two possibilities:
The flag is cleared by the 2-step sequence described in
10.7
The TPM includes:
Each timer channel has:
Refer to the direct-page register summary in the
assignments for all TPM registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
Some MCU systems have more than one TPM, so register names include placeholder characters to identify
which TPM and which channel is being referenced. For example, TPMxCnSC refers to timer (TPM) x,
channel n and TPM1C2SC is the status and control register for timer 1, channel 2.
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When the channel is configured for edge-aligned PWM, the channel flag is set when the timer
counter matches the channel value register that marks the end of the active duty cycle period.
When the channel is configured for center-aligned PWM, the timer count matches the channel
value register twice during each PWM cycle. In this CPWM case, the channel flag is set at the start
and at the end of the active duty cycle, which are the times when the timer counter matches the
channel value register.
An 8-bit status and control register (TPMxSC)
A 16-bit counter (TPMxCNTH:TPMxCNTL)
A 16-bit modulo register (TPMxMODH:TPMxMODL)
An 8-bit status and control register (TPMxCnSC)
A 16-bit channel value register (TPMxCnVH:TPMxCnVL)
TPM Registers and Control Bits
PWM End-of-Duty-Cycle Events
MC9S08GB60A Data Sheet, Rev. 2
Memory
Section 10.6.1, “Clearing Timer Interrupt
chapter of this data sheet for the absolute address
Freescale Semiconductor
Flags.”
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