MC9S08GT60ACFDE Freescale, MC9S08GT60ACFDE Datasheet - Page 109

• Manufacturer Part Number: MC9S08GT60ACFDE
• Manufacturer: Freescale

Specifications of MC9S08GT60ACFDE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8/2.08V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: QFN EP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

7.3
This section provides a functional description of each of the five operating modes of the ICG. Also covered
are the loss of clock and loss of lock errors and requirements for entry into each mode. The ICG is very
flexible, and in some configurations, it is possible to exceed certain clock specifications. When using the
FLL, configure the ICG so that the frequency of ICGDCLK does not exceed its maximum value to ensure
proper MCU operation.
7.3.1
Normally when the CPU enters stop mode, the ICG will cease all clock activity and is in the off state.
However there are two cases to consider when clock activity continues while the CPU is in stop mode.
7.3.1.1
When the BDM is enabled (ENBDM = 1), the ICG continues activity as originally programmed. This
allows access to memory and control registers via the BDC.
7.3.1.2
When the oscillator is enabled in stop mode (OSCSTEN = 1), the individual clock generators are enabled
but the clock feed to the rest of the MCU is turned off. This option is provided to avoid long oscillator
startup times if necessary, or to run the RTI from the oscillator during stop3.
7.3.1.3
Upon the CPU exiting stop mode due to an interrupt, the previously set control bits are valid and the system
clock feed resumes. If FEE is selected, the ICG will source the internal reference until the external clock
is stable. If FBE is selected, the ICG will wait for the external clock to stabilize before enabling ICGOUT.
Upon the CPU exiting stop mode due to a reset, the previously set ICG control bits are ignored and the
default reset values applied. Therefore the ICG will exit stop in SCM mode configured for an
approximately 8 MHz DCO output (4 MHz bus clock) with trim value maintained. If using a crystal, 4096
clocks are detected prior to engaging ICGERCLK. This is incorporated in crystal start-up time.
7.3.2
Self-clocked mode (SCM) is the default mode of operation and is entered when any of the following
conditions occur:
Freescale Semiconductor
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After any reset.
Exiting from off mode when CLKS does not equal 10. If CLKS = X1, the ICG enters this state
temporarily until the DCO is stable (DCOS = 1).
CLKS bits are written from X1 to 00.
CLKS = 1X and ICGERCLK is not detected (both ERCS = 0 and LOCS = 1).
Functional Description
Off Mode (Off)
Self-Clocked Mode (SCM)
OSCSTEN Bit Set
Stop/Off Mode Recovery
BDM Active
MC9S08GB60A Data Sheet, Rev. 2
Internal Clock Generator (S08ICGV2)
109