MC68HC908QT2CPE Freescale, MC68HC908QT2CPE Datasheet - Page 111

• Manufacturer Part Number: MC68HC908QT2CPE
• Manufacturer: Freescale

Specifications of MC68HC908QT2CPE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 128Byte
• # I/os (max): 6
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 4-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 8
• Package Type: PDIP
• Program Memory Type: Flash
• Program Memory Size: 1.5KB
• Lead Free Status / RoHS Status: Compliant

13.6.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after
completion of the current instruction. When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the condition code register), and if the
corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is
serviced first.
is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the
LDA instruction is executed.
The LDA opcode is prefetched by both the INT1 and INT2 return-from-interrupt (RTI) instructions.
However, in the case of the INT1 RTI prefetch, this is a redundant operation.
Freescale Semiconductor
ADDRESS BUS
ADDRESS BUS
INTERRUPT
INTERRUPT
DATA BUS
DATA BUS
MODULE
MODULE
I BIT
I BIT
R/W
R/W
Figure 13-10
To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, software
should save the H register and then restore it prior to exiting the routine.
DUMMY
DUMMY
demonstrates what happens when two interrupts are pending. If an interrupt
SP – 4
SP
PC – 1[7:0] PC – 1[15:8]
MC68HC908QY/QT Family Data Sheet, Rev. 6
CCR
Figure 13-9. Interrupt Recovery
SP – 1
Figure 13-8
SP – 3
A
SP – 2
SP – 2
NOTE
.
X
Interrupt Entry
X
SP – 3
SP – 1
PC – 1[7:0] PC – 1[15:8] OPCODE
A
SP – 4
SP
CCR
VECT H
PC
V DATA H
VECT L
PC + 1
V DATA L
OPERAND
START ADDR
Exception Control
OPCODE
111