MC68HC908QT2CPE Freescale, MC68HC908QT2CPE Datasheet - Page 87

• Manufacturer Part Number: MC68HC908QT2CPE
• Manufacturer: Freescale

Specifications of MC68HC908QT2CPE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 128Byte
• # I/os (max): 6
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 4-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 8
• Package Type: PDIP
• Program Memory Type: Flash
• Program Memory Size: 1.5KB
• Lead Free Status / RoHS Status: Compliant

10.4 LVI Status Register
The LVI status register (LVISR) indicates if the V
LVI resets have been disabled
LVIOUT — LVI Output Bit
10.5 LVI Interrupts
The LVI module does not generate interrupt requests.
10.6 Low-Power Modes
The STOP and WAIT instructions put the MCU in low power-consumption standby modes.
10.6.1 Wait Mode
If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can
generate a reset and bring the MCU out of wait mode.
10.6.2 Stop Mode
When the LVIPWRD bit in the configuration register is cleared and the LVISTOP bit in the configuration
register is set, the LVI module remains active in stop mode. If enabled to generate resets, the LVI module
can generate a reset and bring the MCU out of stop mode.
Freescale Semiconductor
This read-only flag becomes set when the V
when V
that prevents oscillation into and out of reset (see
DD
Address: $FE0C
voltage rises above V
Reset:
Read:
Write:
LVIOUT
Bit 7
0
= Unimplemented
.
Figure 10-2. LVI Status Register (LVISR)
V
TRIPF
MC68HC908QY/QT Family Data Sheet, Rev. 6
6
0
0
V
Table 10-1. LVIOUT Bit Indication
V
TRIPR
DD
DD
< V
V
> V
< V
DD
DD
. The difference in these threshold levels results in a hysteresis
TRIPR
TRIPF
5
0
0
< V
TRIPR
DD
DD
voltage falls below the V
4
0
0
voltage was detected below the V
Table
Previous value
10-1). Reset clears the LVIOUT bit.
R
3
0
0
LVIOUT
0
1
= Reserved
2
0
0
TRIPF
1
0
0
trip voltage and is cleared
Bit 0
TRIPF
R
0
LVI Status Register
level while
87