MC68HC908QT2CPE Freescale, MC68HC908QT2CPE Datasheet - Page 141

MC68HC908QT2CPE

Manufacturer Part Number
MC68HC908QT2CPE
Description
Manufacturer
Freescale
Datasheet

Specifications of MC68HC908QT2CPE

Cpu Family
HC08
Device Core Size
8b
Frequency (max)
8MHz
Total Internal Ram Size
128Byte
# I/os (max)
6
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
4-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
8
Package Type
PDIP
Program Memory Type
Flash
Program Memory Size
1.5KB
Lead Free Status / RoHS Status
Compliant
Simple monitor commands can access any memory address. In monitor mode, the MCU can execute
code downloaded into RAM by a host computer while most MCU pins retain normal operating mode
functions. All communication between the host computer and the MCU is through the PTA0 pin. A
level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used
in a wired-OR configuration and requires a pullup resistor.
The monitor code has been updated from previous versions of the monitor code to allow enabling the
internal oscillator to generate the internal clock. This addition, which is enabled when IRQ is held low out
of reset, is intended to support serial communication/programming at 9600 baud in monitor mode by using
the internal oscillator, and the internal oscillator user trim value OSCTRIM (FLASH location $FFC0, if
programmed) to generate the desired internal frequency (3.2 MHz). Since this feature is enabled only
when IRQ is held low out of reset, it cannot be used when the reset vector is programmed (i.e., the value
is not $FFFF) because entry into monitor mode in this case requires V
remain low during this monitor session in order to maintain communication.
Table 15-1
may be entered after a power-on reset (POR) and will allow communication at 9600 baud provided one
of the following sets of conditions is met:
Freescale Semiconductor
2
3
5
1 μF
1 μF
DB9
If $FFFE and $FFFF do not contain $FF (programmed state):
If $FFFE and $FFFF contain $FF (erased state):
If $FFFE and $FFFF contain $FF (erased state):
The external clock is 9.8304 MHz
IRQ = V
The external clock is 9.8304 MHz
IRQ = V
IRQ = V
+
+
shows the pin conditions for entering monitor mode. As specified in the table, monitor mode
1
3
4
5
7
8
C1+
C1–
C2+
C2–
Figure 15-12. Monitor Mode Circuit (Internal Clock, No High Voltage)
TST
DD
SS
MAX232
(internal oscillator is selected, no external clock required)
(this can be implemented through the internal IRQ pullup)
V+
V–
16
15
2
10
6
1 μF
9
MC68HC908QY/QT Family Data Sheet, Rev. 6
V
DD
+
+
1 μF
2
74HC125
1
+
3
1 μF
74HC125
6
4
10 kΩ
5
V
DD
10 kΩ
*
* Value not critical
N.C.
N.C.
RST (PTA3)
OSC1 (PTA5)
IRQ (PTA2)
PTA0
TST
on IRQ. The IRQ pin must
Monitor Module (MON)
PTA1
PTA4
V
V
DD
SS
V
N.C.
N.C.
DD
0.1 μF
141

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