MC68HC908QT2CPE Freescale, MC68HC908QT2CPE Datasheet - Page 98

• Manufacturer Part Number: MC68HC908QT2CPE
• Manufacturer: Freescale

Specifications of MC68HC908QT2CPE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 128Byte
• # I/os (max): 6
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 4-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 8
• Package Type: PDIP
• Program Memory Type: Flash
• Program Memory Size: 1.5KB
• Lead Free Status / RoHS Status: Compliant

Input/Output Ports (PORTS)
12.2.1 Port A Data Register
The port A data register (PTA) contains a data latch for each of the six port A pins.
PTA[5:0] — Port A Data Bits
AWUL — Auto Wakeup Latch Data Bit
KBI[5:0] — Port A Keyboard Interrupts
12.2.2 Data Direction Register A
Data direction register A (DDRA) determines whether each port A pin is an input or an output. Writing a 1
to a DDRA bit enables the output buffer for the corresponding port A pin; a 0 disables the output buffer.
DDRA[5:0] — Data Direction Register A Bits
98
These read/write bits are software programmable. Data direction of each port A pin is under the control
of the corresponding bit in data direction register A. Reset has no effect on port A data.
This is a read-only bit which has the value of the auto wakeup interrupt request latch. The wakeup
request signal is generated internally (see
port nor any of the associated bits such as PTA6 data register, pullup enable or direction.
The keyboard interrupt enable bits, KBIE5–KBIE0, in the keyboard interrupt control enable register
(KBIER) enable the port A pins as external interrupt pins (see
(KBI)).
These read/write bits control port A data direction. Reset clears DDRA[5:0], configuring all port A pins
as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
Additional Functions:
Address: $0004
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Reset:
Read:
Write:
Address: $0000
Reset:
Read:
Write:
Bit 7
R
R
0
Figure 12-2. Data Direction Register A (DDRA)
Bit 7
R
R
= Reserved
Figure 12-1. Port A Data Register (PTA)
MC68HC908QY/QT Family Data Sheet, Rev. 6
R
6
0
= Reserved
AWUL
6
DDRA5
5
0
Chapter 4 Auto Wakeup Module
PTA5
KBI5
5
NOTE
DDRA4
4
0
Unaffected by reset
PTA4
KBI4
4
= Unimplemented
DDRA3
3
0
= Unimplemented
PTA3
KBI3
3
Chapter 9 Keyboard Interrupt Module
2
0
0
PTA2
KBI2
2
DDRA1
(AWU)). There is no PTA6
1
0
PTA1
KBI1
1
Freescale Semiconductor
DDRA0
Bit 0
0
PTA0
KBI0
Bit 0