MC68HC908QT2CPE Freescale, MC68HC908QT2CPE Datasheet - Page 137

• Manufacturer Part Number: MC68HC908QT2CPE
• Manufacturer: Freescale

Specifications of MC68HC908QT2CPE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 128Byte
• # I/os (max): 6
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 4-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 8
• Package Type: PDIP
• Program Memory Type: Flash
• Program Memory Size: 1.5KB
• Lead Free Status / RoHS Status: Compliant

15.2.2.3 Break Auxiliary Register
The break auxiliary register (BRKAR) contains a bit that enables software to disable the COP while the
MCU is in a state of break interrupt with monitor mode.
BDCOP — Break Disable COP Bit
15.2.2.4 Break Status Register
The break status register (BSR) contains a flag to indicate that a break caused an exit from wait mode.
This register is only used in emulation mode.
SBSW — SIM Break Stop/Wait
Freescale Semiconductor
This read/write bit disables the COP during a break interrupt. Reset clears the BDCOP bit.
SBSW can be read within the break state SWI routine. The user can modify the return address on the
stack by subtracting one from it.
1 = COP disabled during break interrupt
0 = COP enabled during break interrupt
1 = Wait mode was exited by break interrupt
0 = Wait mode was not exited by break interrupt
Address: $FE02
Address: $FE00
Reset:
Reset:
Read:
Read:
Write:
Write:
Bit 7
Bit 7
R
R
0
0
Figure 15-6. Break Auxiliary Register (BRKAR)
= Unimplemented
= Reserved
Figure 15-7. Break Status Register (BSR)
MC68HC908QY/QT Family Data Sheet, Rev. 6
0
R
6
0
6
R
5
0
0
5
R
4
0
0
4
1. Writing a 0 clears SBSW.
R
3
0
0
3
R
2
0
0
2
Note
SBSW
1
0
0
1
0
(1)
BDCOP
Bit 0
Bit 0
Break Module (BRK)
R
0
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