MC68HC908QT2CPE Freescale, MC68HC908QT2CPE Datasheet - Page 31

• Manufacturer Part Number: MC68HC908QT2CPE
• Manufacturer: Freescale

Specifications of MC68HC908QT2CPE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 128Byte
• # I/os (max): 6
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 4-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 8
• Package Type: PDIP
• Program Memory Type: Flash
• Program Memory Size: 1.5KB
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor
$FE0C
$FE0D
$FFBE
$FE08
$FE09
$FE0A
$FE0B
$FE0F
$FFBF
$FFC0
$FFC1
$FFFF
Addr.
↓
Reserved for FLASH Test
Break Status and Control
FLASH Control Register
Internal Oscillator Trim
Internal Oscillator Trim
(Factory Programmed,
(Factory Programmed,
COP Control Register
Register Name
FLASH Block Protect
Break Address High
Register (BRKSCR)
LVI Status Register
Break Address low
Register (FLBPR)
Register (BRKH)
Register (BRKL)
See page 136.
See page 136.
See page 136.
See page 34.
See page 87.
See page 39.
VDD = 5.0 V)
VDD = 3.0 V)
See page 59.
(COPCTL)
Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 5)
(LVISR)
(FLCR)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
MC68HC908QY/QT Family Data Sheet, Rev. 6
LVIOUT
TRIM7
TRIM7
BRKE
BPR7
Bit 15
Bit 7
Bit 7
R
R
0
0
0
0
0
0
= Unimplemented
TRIM6
TRIM6
BRKA
Bit 14
BPR6
Bit 6
R
R
6
0
0
0
0
0
0
0
WRITING CLEARS COP COUNTER (ANY VALUE)
TRIM5
TRIM5
Bit 13
BPR5
Bit 5
R
R
5
0
0
0
0
0
0
0
0
LOW BYTE OF RESET VECTOR
TRIM4
TRIM4
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
Bit 12
BPR4
Bit 4
R
R
R
4
0
0
0
0
0
0
0
0
= Reserved
TRIM3
TRIM3
HVEN
BPR3
Bit 11
Bit 3
R
R
3
0
0
0
0
0
0
0
TRIM2
TRIM2
MASS
Bit 10
BPR2
U = Unaffected
Bit 2
R
R
Input/Output (I/O) Section
2
0
0
0
0
0
0
0
ERASE
TRIM1
TRIM1
BPR1
Bit 9
Bit 1
R
R
1
0
0
0
0
0
0
0
TRIM0
TRIM0
BPR0
PGM
Bit 0
Bit 8
Bit 0
R
R
R
0
0
0
0
0
0
31