MAX1359BETL+ Maxim Integrated Products, MAX1359BETL+ Datasheet - Page 25

• Manufacturer Part Number: MAX1359BETL+
• Description: IC DAS 16BIT 40-TQFN
• Manufacturer: Maxim Integrated Products
• Type: Data Acquisition System (DAS)r

Specifications of MAX1359BETL+

• Resolution (bits): 16 b
• Sampling Rate (per Second): 21.84k
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Number Of Converters: 2
• Resolution: 16 bit
• Interface Type: Serial (4-Wire, SPI, QSPI, Microwire)
• Voltage Reference: 1.25 V
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.8 V
• Maximum Power Dissipation: 2051.3 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 1.8 V to 3.6 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

the system or cause an interrupt at a predefined time.
The power-supply voltage monitor detects when DV
falls below a trip threshold voltage of +1.8V, asserting
RESET. The MAX1359B uses a 4-wire serial interface to
communicate directly between SPI, QSPI, or
MICROWIRE devices for system configuration and
readback functions.
The MAX1359B includes a sigma-delta ADC with pro-
grammable conversion rate, a PGA, and a dual 10:1
input mux. When performing continuous conversions at
10sps or single conversions at the 40sps setting (effec-
tively 10sps due to four sample sigma-delta settling),
the ADC has 16-bit noise-free resolution. The noise-free
resolution drops to 10 bits at the maximum sampling
rate of 512sps. Differential inputs support unipolar
(between 0 and V
modes of operation. Note: Avoid combinations of input
signal and PGA gains that exceed the reference range
at the ADC input. The ADOU bit in the status register
indicates if the ADC has over-ranged or under-ranged.
Zero-scale and full-scale calibrations remove offset and
gain errors. Direct access to gain and zero-scale cali-
bration registers allows system-level offset and gain cal-
ibration. The zero-scale adjustment register allows
intentional positive offset skewing to preserve unipolar-
mode resolution for signals that have a slight negative
offset (i.e., unipolar clipping near zero can be removed).
Perform ADC calibration whenever the ADC configura-
tion, temperature, or AV
tus can be programmed to provide an interrupt on INT
or on any UPIO_.
An integrated PGA provides four selectable gains: +1V/V,
+2V/V, +4V/V, and +8V/V to maximize the dynamic range
of the ADC. Bits GAIN1 and GAIN0 set the gain (see the
ADC Register for more information). The PGA gain is
implemented in the digital filter of the ADC.
The MAX1359B performs analog-to-digital conversions
using a single-bit, 3rd-order, switched-capacitor sigma-
delta modulator. The sigma-delta modulation converts
the input signal into a digital pulse train whose average
duty cycle represents the digitized signal information.
The pulse train is then processed by a digital decimation
filter. The modulator provides 2nd-order frequency shap-
ing of the quantization noise resulting from the single-bit
quantizer. The modulator is fully differential for maximum
signal-to-noise ratio and minimum susceptibility to
power-supply noise.
UPIOs, RTC, Voltage Monitors, and Temp Sensor
16-Bit, Data-Acquisition System with ADC, DAC,
Analog-to-Digital Converter (ADC)
______________________________________________________________________________________
REF
) and bipolar (between ±V
DD
changes. The ADC-done sta-
ADC Modulator
PGA Gain
REF
DD
)
INT asserts (and remains asserted) within 30µs when
the differential voltage on the selected analog inputs
exceeds the signal-detect comparator trip threshold.
The signal-detect comparator’s differential input trip
threshold (i.e., offset) is user selectable and can be pro-
grammed to the following values: 0mV, 50mV, 100mV,
150mV, or 200mV.
The ADC provides two external analog inputs: AIN1
and AIN2. The rail-to-rail inputs accept differential or
single-ended voltages, or external temperature-sensing
diodes. The unused op amps, switches, or DAC inputs
and output pins can also be used as rail-to-rail analog
inputs if the associated function is disabled.
Internal protection diodes clamp the analog inputs to
AV
from (AGND - 0.3V) to (AV
conversions near full scale, the inputs must not exceed
AV
50mV. If the inputs exceed (AGND - 0.3V) to (AV
0.3V), limit the current to 50mA.
The MAX1359B includes a dual 10:1 mux for the positive
and negative inputs of the ADC. Figure 3 illustrates which
signals are present at the inputs of each mux. The
MUXP[3:0] and MUXN[3:0] bits of the mux register select
the input to the ADC and the signal-detect comparator
(Tables 8 and 9). See the mux register description in the
Register Definitions section for multiplexer functionality.
The POL bit of the ADC register swaps the polarity of mux
output signals to the ADC.
The MAX1359B contains an on-chip digital lowpass fil-
ter that processes the data stream from the modulator
using a SINC
settling time of four output data periods (4 x 200ms).
The MAX1359B has 25% overrange capability built into
the modulator and digital filter:
Figure 4 shows the filter frequency response. The
SINC
times the first notch frequency.
DD
DD
4
and AGND, and allow the channel input to swing
by more than 50mV or be lower than AGND by
characteristic -3dB cutoff frequency is 0.228
4
(sinx/x)
H f
( ) =
⎡
⎢
⎢
⎢
⎢
⎢
⎣
4
Signal-Detect Comparator
N
1
response. The SINC
SIN N
SIN
DD
⎛
⎜
⎝
⎛
⎜
⎝
Analog Input Protection
π
π
f
+ 0.3V). For accurate
m
f
f
m
f
⎞
⎟
⎠
⎞
⎟
⎠
Digital Filtering
⎤
⎥
⎥
⎥
⎥
⎥
⎦
Analog Inputs
4
Analog Mux
4
filter has a
DD
25
+