MAX1359BETL+ Maxim Integrated Products, MAX1359BETL+ Datasheet - Page 40
![IC DAS 16BIT 40-TQFN](/photos/6/65/66502/40-qfn_pkg_sml.jpg)
MAX1359BETL+
Manufacturer Part Number
MAX1359BETL+
Description
IC DAS 16BIT 40-TQFN
Manufacturer
Maxim Integrated Products
Type
Data Acquisition System (DAS)r
Specifications of MAX1359BETL+
Resolution (bits)
16 b
Sampling Rate (per Second)
21.84k
Data Interface
Serial
Voltage Supply Source
Analog and Digital
Voltage - Supply
1.8 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
40-TQFN Exposed Pad
Number Of Converters
2
Resolution
16 bit
Interface Type
Serial (4-Wire, SPI, QSPI, Microwire)
Voltage Reference
1.25 V
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.8 V
Maximum Power Dissipation
2051.3 mW
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Input Voltage
1.8 V to 3.6 V
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
The AL_DAY register stores the second information of
the time-of-day alarm.
ASEC<19:0>: Alarm-second bits. These 20 bits store
the time-of-day alarm, which corresponds to the lower
20 bits of the RTC second counter or SEC<19:0>.
Program the time-of-day alarm trigger between 1s to
just over 12 days beyond the current RTC second
counter value in increments of 1s.
Assert the AWE bit in the CLK_CTRL register (see the
CLK_CTRL Register section) to enable writing to the
AL_DAY register. Enabling the time-of-day alarm requires
two writes to the CLK_CTRL register. Write the 20 alarm-
second bits in 3 bytes, MSB first. If CS is raised before
the LSB is written, the alarm write is aborted, and the
existing value remains. When the lower 20 bits in the RTC
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
AL_DAY Register (Power-On State: 0000 0000 0000 0000 0000 XXXX)
40
ASEC19
ASEC11
ASEC3
______________________________________________________________________________________
MSB
ASEC18
ASEC10
ASEC2
ASEC17
ASEC9
ASEC1
ASEC16
ASEC8
ASEC0
second counter match the contents of this register, the
alarm triggers and asserts ALD in the STATUS register. It
also asserts an interrupt on the INT pin unless masked by
the MALD bit in the IMSK register. The part enters normal
mode if an alarm triggers while in sleep mode. The time-
of-day alarm is intended to trigger single events.
Therefore, once it triggers, in the CLK_CTRL register, the
ADE bit is automatically cleared, disabling the time-of-
day alarm. Implement a recurring alarm with repeated
software writes over the serial interface each time the
time-of-day alarm triggers. The time-of-day alarm can
also be programmed to output at the UPIO pins.
When configured this way the MALD bit does not mask
the UPIO alarm output.
ASEC15
ASEC7
X
ASEC14
ASEC6
X
ASEC13
ASEC5
X
ASEC12
ASEC4
LSB
X