MAX1359BETL+ Maxim Integrated Products, MAX1359BETL+ Datasheet - Page 31

• Manufacturer Part Number: MAX1359BETL+
• Description: IC DAS 16BIT 40-TQFN
• Manufacturer: Maxim Integrated Products
• Type: Data Acquisition System (DAS)r

Specifications of MAX1359BETL+

• Resolution (bits): 16 b
• Sampling Rate (per Second): 21.84k
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Number Of Converters: 2
• Resolution: 16 bit
• Interface Type: Serial (4-Wire, SPI, QSPI, Microwire)
• Voltage Reference: 1.25 V
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.8 V
• Maximum Power Dissipation: 2051.3 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 1.8 V to 3.6 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3) Repeat steps 1 and 2 with I
The measured temperature is defined as follows:
where V
For an external temperature sensor, either the two-cur-
rent or four-current method can be used. Connect an
external diode (such as 2N3904 or 2N3906) between
pins AIN1 and AGND (or AIN2 and AGND). Connect a
sense resistor R between AIN1 and AIN2. Maximize R
so the IR drop plus V
60µA)+V
or (AV
temperature sensor can be used for the external tem-
perature sensor, by routing the currents to AIN1 (or
AIN2) (see Table 20).
For the two-current method, if the external diode’s
series resistance (R
measurement can be corrected as shown below:
To account for various error sources during the temper-
ature measurement, the internal temperature sensor is
calibrated at the factory. The calibrated temperature
equation is shown below:
where g and b are the gain and offset calibration val-
ues, respectively. These calibration values are available
for reading from the TEMP_CAL register.
An internal 1.25V bandgap reference has a buffer with
a selectable 1.0V/V, 1.638V/V, or 2.0V/V gain, resulting
in a respective 1.25V, 2.048V, or 2.5V reference voltage
at REF. The ADC and DAC use this reference voltage.
The state of the internal voltage reference output buffer at
POR is disabled so it can be driven, at REF, with an exter-
nal reference between AGND and AV
has an initial tolerance of ±3%. Program the reference
T
T
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MEAS
ACTUAL
16-Bit, Data-Acquisition System with ADC, DAC,
DD
=
REF
BE
=
- 400mV). The same procedure as the internal
q N
M
M
T
(
MEAS
] is the smaller of the ADC reference voltage
2
1
is the reference voltage used and:
VBE
=
⎛
⎜
⎝
−
N
3
⎛
⎜
⎜
⎜
⎜
⎝
N
Voltage Reference and Buffer
T
9
V
______________________________________________________________________________________
−
V
(
A
3
N
1
N
S
V
−
−
= g x T
Temperature-Sensor Calibration
VBE
) is known, then the temperature
2
N
N
nkIn
−
nkIn
VBE
VBE
External Temperature Sensor
N
BE
1
VBE
)
⎛
⎜
⎝
N
−
⎛
⎜
⎝
N
1
3
MEAS
of the p-n junction [(R x
2
V
M
V
q N
M
⎞
⎟
⎠
)
2
1
(
2
2
−
1
⎛
⎜
⎝
−
−
, I
9
N
N
⎞
⎟
⎠
N
N
VBE
(
N
VBE
3
V
V
VBE
+ b
V
, and I
4
2
1
4
1
1
−
−
−
⎞
⎟
⎠
N
−
DD
N
N
VBE
N
VBE
VBE
. The reference
4
VBE
1
.
)
2
4
×
2
⎞
⎟
⎠
V
2
)
REF
16
×
V
×
2
REF
16
R
R
S
⎞
⎟
⎟
⎟
⎟
⎠
buffer through the serial interface. Bypass REF with a
4.7µF capacitor to AGND.
The MAX1359B includes two op amps. These op amps
feature rail-to-rail outputs, near rail-to-rail inputs, and have
an 80kHz (1nF load) input bandwidth. The DACA_OP
(DACB_OP) register controls the power state of the op
amps. When powered down, the outputs of the op amps
are high impedance.
The MAX1359B provides two uncommitted SPDT switch-
es. Each switch has a typical on-resistance of 35Ω.
Control the switches through the SW_CTRL register, the
PWM output, and/or a UPIO port configured to control the
switches (UPIO1–UPIO4_CTRL register).
A single 8-bit PWM is available for various system tasks
such as LCD bias control, sensor bias voltage trim,
buzzer drive, and duty-cycled sleep-mode power-con-
trol schemes. PWM input clock sources include the
4.9512MHz FLL output, the 32kHz clock, and frequen-
cy-divided versions of each. Although most µCs have
built-in PWM functions, the MAX1359B PWM is more
flexible by allowing the UPIO outputs to be driven to
DV
For duty-cycled power-control schemes, use the
32kHz-derived input clock. The PWM output is available
independent of µC power state. The FLL is typically dis-
abled in sleep-override mode.
The MAX1359B features a 4-wire serial interface consist-
ing of a chip select (CS), serial clock (SCLK), data in
(DIN), and data out (DOUT). CS must be low to allow data
to be clocked into or out of the device. DOUT is high
impedance while CS is high. The data is clocked in at
DIN on the rising edge of SCLK. Data is clocked out at
DOUT on the falling edge of SCLK. The serial interface is
compatible with SPI modes CPOL = 0, CPHA = 0 and
CPOL = 1, CPHA = 1. A write operation to the MAX1359B
takes effect on the last rising edge of SCLK. If CS goes
high before the complete transfer, the write is ignored.
Every data transfer is initiated by the command byte. The
command byte consists of a start bit (MSB), R/W bit, and
6 address bits. The start bit must be 1 to perform data
transfers to the device. Zeros clocked in are ignored. For
SPI passthrough mode, see the UPIO_SPI register . An
address byte identifies each register. Table 4 shows the
complete register address map for this family of DAS.
Figures 14, 15, and 16 provide timing diagrams for read
and write commands.
Single-Pole/Double-Throw (SPDT) Switches
DD
or regulated CPOUT logic-high voltage levels.
Operational Amplifiers (Op Amps)
Pulse-Width Modulator (PWM)
Serial Interface
31