MT41J256M8HX-15E IT:D Micron Technology Inc, MT41J256M8HX-15E IT:D Datasheet - Page 10

• Manufacturer Part Number: MT41J256M8HX-15E IT:D
• Description: MICMT41J256M8HX-15E_IT:D 2GB DDR3 SDRAM
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J256M8HX-15E IT:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: -40C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

2Gb: x4, x8, x16 DDR3 SDRAM
Figure 103: ACTIVATE to Power-Down Entry ................................................................................................ 185
Figure 104: PRECHARGE to Power-Down Entry ............................................................................................. 185
Figure 105: MRS Command to Power-Down Entry ........................................................................................ 186
Figure 106: Power-Down Exit to Refresh to Power-Down Entry ...................................................................... 186
Figure 107: RESET Sequence ........................................................................................................................ 188
Figure 108: On-Die Termination ................................................................................................................... 189
Figure 109: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 .................................................... 193
Figure 110: Dynamic ODT: Without WRITE Command .................................................................................. 193
Figure 111: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 ........... 194
Figure 112: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 ......................... 195
Figure 113: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 ......................... 195
Figure 114: Synchronous ODT ...................................................................................................................... 197
Figure 115: Synchronous ODT (BC4) ............................................................................................................. 198
Figure 116: ODT During READs .................................................................................................................... 200
Figure 117: Asynchronous ODT Timing with Fast ODT Transition .................................................................. 202
Figure 118: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry ........... 204
Figure 119: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit .............. 206
Figure 120: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping .................... 208
Figure 121: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping ................... 209
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2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
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