MT41J256M8HX-15E IT:D Micron Technology Inc, MT41J256M8HX-15E IT:D Datasheet - Page 193

• Manufacturer Part Number: MT41J256M8HX-15E IT:D
• Description: MICMT41J256M8HX-15E_IT:D 2GB DDR3 SDRAM
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J256M8HX-15E IT:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: -40C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

Figure 109: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4
DQS, DQS#
Figure 110: Dynamic ODT: Without WRITE Command
DQS, DQS#
Command
Command
Address
Address
ODT
CK#
DQ
R
CK
ODT
TT
CK#
DQ
R
CK
TT
NOP
T0
Valid
T0
NOP
T1
Valid
T1
Notes:
Notes:
NOP
T2
ODTL on
ODTH4
Valid
NOP
T3
T2
1. Via MRS or OTF. AL = 0, CWL = 5. R
2. ODTH4 applies to first registering ODT HIGH and then to the registration of the WRITE command. In this example,
1. AL = 0, CWL = 5. R
2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW; in this example, ODTH4 is satisfied. ODT
ODTH4 is satisfied if ODT goes LOW at T8 (four clocks after the WRITE command).
ODTL on
registered LOW at T5 is also legal.
t AON (MIN)
t AON (MAX)
WRS4
Valid
T4
ODTH4
Valid
T3
t AON (MIN)
t AON (MAX)
NOP
T5
ODTL
Valid
R
cnw
TT,nom
T4
ODTH4
NOP
T6
TT,nom
WL
Valid
NOP
T7
is enabled and R
T5
ODTL
cwn
t ADC (MIN)
t ADC (MAX)
NOP
4
T8
Valid
T6
TT,nom
NOP
T9
DI
n
R
TT(WR)
TT(WR)
and R
n + 1
DI
Valid
T7
NOP
T10
n + 2
DI
R
TT(WR)
is either enabled or disabled.
TT,nom
n + 3
DI
Valid
NOP
T11
are enabled.
T8
ODTL off
t ADC (MIN)
t ADC (MAX)
T12
NOP
t AOF (MIN)
Valid
T9
t AOF (MAX)
Transitioning
NOP
T13
Valid
T10
R
TT,nom
NOP
T14
ODTL off
Don’t Care
Transitioning
Valid
T15
NOP
T11
NOP
T16
Don’t Care
t AOF (MIN)
t AOF (MAX)
NOP
T17