MT41J256M8HX-15E IT:D Micron Technology Inc, MT41J256M8HX-15E IT:D Datasheet - Page 196

• Manufacturer Part Number: MT41J256M8HX-15E IT:D
• Description: MICMT41J256M8HX-15E_IT:D 2GB DDR3 SDRAM
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J256M8HX-15E IT:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: -40C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

Synchronous ODT Mode
ODT Latency and Posted ODT
Timing Parameters
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
Synchronous ODT mode is selected whenever the DLL is turned on and locked and
when either R
modes are:
• Any bank active with CKE HIGH
• Refresh mode with CKE HIGH
• Idle mode with CKE HIGH
• Active power-down mode (regardless of MR0[12])
• Precharge power-down mode if DLL is enabled during precharge power-down by
In synchronous ODT mode, R
HIGH by a rising clock edge and turns off ODTL off clock cycles after ODT is registered
LOW by a rising clock edge. The actual on/off times varies by
each clock edge (see Table 88 (page 197)). The ODT latency is tied to the WRITE latency
(WL) by ODTL on = WL - 2 and ODTL off = WL - 2.
Since write latency is made up of CAS WRITE latency (CWL) and ADDITIVE latency
(AL), the AL programmed into the mode register (MR1[4, 3]) also applies to the ODT
signal. The device’s internal ODT signal is delayed a number of clock cycles defined by
the AL relative to the external ODT signal. Thus ODTL on = CWL + AL - 2 and ODTL off =
CWL + AL - 2.
Synchronous ODT mode uses the following timing parameters: ODTL on, ODTL off,
ODTH4, ODTH8,
point at which the device leaves High-Z and ODT resistance begins to turn on. Maxi-
mum R
Both are measured relative to ODTL on. The minimum R
is the point at which the device starts to turn off ODT resistance. Maximum R
time (
from ODTL off.
When ODT is asserted, it must remain HIGH until ODTH4 is satisfied. If a WRITE com-
mand is registered by the DRAM with ODT HIGH, then ODT must remain HIGH until
ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (see Figure 115 (page 198)).
ODTH4 and ODTH8 are measured from ODT registered HIGH to ODT registered LOW
or from the registration of a WRITE command until ODT is registered LOW.
MR0[12]
t
AOF [MAX]) is the point at which ODT has reached High-Z. Both are measured
TT
turn-on time (
TT,nom
t
AON, and
or R
t
TT(WR)
AON [MAX]) is the point at which ODT resistance is fully on.
t
196
AOF. The minimum R
TT
is enabled. Based on the power-down definition, these
turns on ODTL on clock cycles after ODT is sampled
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2Gb: x4, x8, x16 DDR3 SDRAM
TT
turn-on time (
Synchronous ODT Mode
TT
turn-off time (
t
© 2006 Micron Technology, Inc. All rights reserved.
AON and
t
AON [MIN]) is the
t
AOF around
t
AOF [MIN])
TT
turn off