MT41J256M8HX-15E IT:D Micron Technology Inc, MT41J256M8HX-15E IT:D Datasheet - Page 8

• Manufacturer Part Number: MT41J256M8HX-15E IT:D
• Description: MICMT41J256M8HX-15E_IT:D 2GB DDR3 SDRAM
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J256M8HX-15E IT:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: -40C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

List of Figures
Figure 1: DDR3 Part Numbers ......................................................................................................................... 2
Figure 2: Simplified State Diagram ................................................................................................................. 11
Figure 3: 512 Meg x 4 Functional Block Diagram ............................................................................................. 14
Figure 4: 256 Meg x 8 Functional Block Diagram ............................................................................................. 15
Figure 5: 128 Meg x 16 Functional Block Diagram ........................................................................................... 15
Figure 6: 78-Ball FBGA – x4, x8 (Top View) ...................................................................................................... 16
Figure 7: 82-Ball FBGA – x4, x8 (Top View) ...................................................................................................... 17
Figure 8: 96-Ball FBGA – x16 (Top View) ......................................................................................................... 18
Figure 9: 78-Ball FBGA – x4, x8; "DA" ............................................................................................................. 25
Figure 10: 78-Ball FBGA – x4, x8; "HX" ............................................................................................................ 26
Figure 11: 82-Ball FBGA – x4, x8; "JE" ............................................................................................................. 27
Figure 12: 96-Ball FBGA – x16; "HA" ............................................................................................................... 28
Figure 13: Thermal Measurement Point ......................................................................................................... 31
Figure 14: Input Signal .................................................................................................................................. 50
Figure 15: Overshoot ..................................................................................................................................... 51
Figure 16: Undershoot .................................................................................................................................. 51
Figure 17: V
Figure 18: Single-Ended Requirements for Differential Signals ........................................................................ 53
Figure 19: Definition of Differential AC-Swing and
Figure 20: Nominal Slew Rate Definition for Single-Ended Input Signals ......................................................... 55
Figure 21: Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# .................................. 56
Figure 22: ODT Levels and I-V Characteristics ................................................................................................ 57
Figure 23: ODT Timing Reference Load .......................................................................................................... 60
Figure 24:
Figure 25:
Figure 26:
Figure 27: Output Driver ............................................................................................................................... 63
Figure 28: DQ Output Signal .......................................................................................................................... 70
Figure 29: Differential Output Signal .............................................................................................................. 71
Figure 30: Reference Output Load for AC Timing and Output Slew Rate .......................................................... 71
Figure 31: Nominal Slew Rate Definition for Single-Ended Output Signals ....................................................... 72
Figure 32: Nominal Differential Output Slew Rate Definition for DQS, DQS# ................................................... 73
Figure 33: Nominal Slew Rate and
Figure 34: Nominal Slew Rate for
Figure 35: Tangent Line for
Figure 36: Tangent Line for
Figure 37: Nominal Slew Rate and
Figure 38: Nominal Slew Rate for
Figure 39: Tangent Line for
Figure 40: Tangent Line for
Figure 41: Refresh Mode ............................................................................................................................... 118
Figure 42: DLL Enable Mode to DLL Disable Mode ........................................................................................ 120
Figure 43: DLL Disable Mode to DLL Enable Mode ........................................................................................ 121
Figure 44: DLL Disable
Figure 45: Change Frequency During Precharge Power-Down ....................................................................... 124
Figure 46: Write Leveling Concept ................................................................................................................ 125
Figure 47: Write Leveling Sequence ............................................................................................................... 128
Figure 48: Exit Write Leveling ....................................................................................................................... 129
Figure 49: Initialization Sequence ................................................................................................................. 131
Figure 50: MRS to MRS Command Timing (
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
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AON and
AONPD and
ADC Definition ............................................................................................................................. 62
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for Differential Signals .............................................................................................................. 52
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AOF Definitions ............................................................................................................ 61
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DQSCK Timing ........................................................................................................ 122
AOFPD Definitions ................................................................................................... 61
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IS (Command and Address – Clock) .................................................................... 103
IH (Command and Address – Clock) ................................................................... 104
DS (DQ – Strobe) ............................................................................................... 110
DH (DQ – Strobe) ............................................................................................... 111
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IH (Command and Address – Clock) .......................................................... 102
DH (DQ – Strobe) ...................................................................................... 109
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VAC for
VAC for
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IS (Command and Address – Clock) ............................................. 101
DS (DQ – Strobe) ........................................................................ 108
MRD) ......................................................................................... 132
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DVAC ............................................................................... 53
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
2Gb: x4, x8, x16 DDR3 SDRAM
© 2006 Micron Technology, Inc. All rights reserved.